From 6c46357c6f1bfeefc3a9f85aed03f94e923d09f1 Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sun, 6 Apr 2008 19:22:15 -0400 Subject: [PATCH] PUSH bugfix --- 7seg.v | 45 +++++++++++++++++++++++++++------------------ CoreTop.ucf | 2 +- GBZ80Core.v | 5 +++-- Makefile | 2 +- System.v | 18 ++++++++++++++---- insn_push_reg.v | 8 ++++---- 6 files changed, 50 insertions(+), 30 deletions(-) diff --git a/7seg.v b/7seg.v index c64e7d5..ba988b0 100644 --- a/7seg.v +++ b/7seg.v @@ -1,8 +1,9 @@ module AddrMon( input [15:0] addr, input clk, + input [3:0] periods, output reg [3:0] digit, - output reg [7:0] out, + output wire [7:0] out, input freeze ); @@ -15,7 +16,14 @@ module AddrMon( (dcount == 2'b00) ? latch[3:0] : (dcount == 2'b01) ? latch[7:4] : (dcount == 2'b10) ? latch[11:8] : - latch[15:12]; + latch[15:12]; + + reg [6:0] odigit; + assign out = {odigit, + ~((dcount == 2'b00) ? periods[0] : + (dcount == 2'b01) ? periods[1] : + (dcount == 2'b10) ? periods[2] : + periods[3]) }; always @ (negedge clk) begin if (clkdv == 31) begin @@ -31,25 +39,26 @@ module AddrMon( case(curval) /* ABCDEFGP */ - 4'h0: out <= ~8'b11111100; - 4'h1: out <= ~8'b01100000; - 4'h2: out <= ~8'b11011010; - 4'h3: out <= ~8'b11110010; - 4'h4: out <= ~8'b01100110; - 4'h5: out <= ~8'b10110110; - 4'h6: out <= ~8'b10111110; - 4'h7: out <= ~8'b11100000; - 4'h8: out <= ~8'b11111110; - 4'h9: out <= ~8'b11110110; - 4'hA: out <= ~8'b11101110; - 4'hB: out <= ~8'b00111110; - 4'hC: out <= ~8'b10011100; - 4'hD: out <= ~8'b01111010; - 4'hE: out <= ~8'b10011110; - 4'hF: out <= ~8'b10001110; + 4'h0: odigit <= ~8'b1111110; + 4'h1: odigit <= ~8'b0110000; + 4'h2: odigit <= ~8'b1101101; + 4'h3: odigit <= ~8'b1111001; + 4'h4: odigit <= ~8'b0110011; + 4'h5: odigit <= ~8'b1011011; + 4'h6: odigit <= ~8'b1011111; + 4'h7: odigit <= ~8'b1110000; + 4'h8: odigit <= ~8'b1111111; + 4'h9: odigit <= ~8'b1111011; + 4'hA: odigit <= ~8'b1110111; + 4'hB: odigit <= ~8'b0011111; + 4'hC: odigit <= ~8'b1001110; + 4'hD: odigit <= ~8'b0111101; + 4'hE: odigit <= ~8'b1001111; + 4'hF: odigit <= ~8'b1000111; endcase end else clkdv <= clkdv + 1; + if (~freeze) latch <= addr; end diff --git a/CoreTop.ucf b/CoreTop.ucf index 6cbca7e..243f9ec 100644 --- a/CoreTop.ucf +++ b/CoreTop.ucf @@ -17,7 +17,7 @@ NET "switches<4>" LOC="l14"; NET "switches<3>" LOC="k17"; NET "switches<2>" LOC="k18"; NET "switches<1>" LOC="h18"; -NET "switches<0>" LOC="g18"; +NET "switches<0>" LOC="g18" | CLOCK_DEDICATED_ROUTE = FALSE; NET "seven<7>" LOC="L18"; NET "seven<6>" LOC="F18"; diff --git a/GBZ80Core.v b/GBZ80Core.v index f438339..36cd76a 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -118,9 +118,10 @@ module GBZ80Core( output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */ inout [7:0] busdata, output reg buswr, output reg busrd, - input irq, input [7:0] jaddr); + input irq, input [7:0] jaddr, + output reg [1:0] state); - reg [1:0] state; /* State within this bus cycle (see STATE_*). */ +// reg [1:0] state; /* State within this bus cycle (see STATE_*). */ reg [2:0] cycle; /* Cycle for instructions. */ reg [7:0] registers[11:0]; diff --git a/Makefile b/Makefile index 175241d..41aff51 100644 --- a/Makefile +++ b/Makefile @@ -9,7 +9,7 @@ VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \ all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr -CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS) CoreTop.ucf +CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS) xst -ifn CoreTop.xst -ofn CoreTop.syr CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf diff --git a/System.v b/System.v index 0afc090..4081771 100644 --- a/System.v +++ b/System.v @@ -71,6 +71,9 @@ module CoreTop( wire clk; CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk)); + + wire cclk; + IBUFG ibuf (.O(cclk), .I(switches[0])); wire [15:0] addr; wire [7:0] data; @@ -78,15 +81,17 @@ module CoreTop( wire irq, tmrirq; wire [7:0] jaddr; + wire [1:0] state; GBZ80Core core( - .clk(clk), + .clk(cclk), .busaddress(addr), .busdata(data), .buswr(wr), .busrd(rd), .irq(irq), - .jaddr(jaddr)); + .jaddr(jaddr), + .state(state)); ROM rom( .address(addr), @@ -100,7 +105,12 @@ module CoreTop( .clk(clk), .digit(digits), .out(seven), - .freeze(buttons[0])); + .freeze(buttons[0]), + .periods( + (state == 2'b00) ? 4'b1000 : + (state == 2'b01) ? 4'b0100 : + (state == 2'b10) ? 4'b0010 : + 4'b0001) ); Switches sw( .address(addr), @@ -109,7 +119,7 @@ module CoreTop( .wr(wr), .rd(rd), .ledout(leds), - .switches(switches) + .switches({switches[7:1],1'b0}) ); UART nouart ( /* no u */ diff --git a/insn_push_reg.v b/insn_push_reg.v index afec70a..6b789e5 100644 --- a/insn_push_reg.v +++ b/insn_push_reg.v @@ -8,10 +8,10 @@ `INSN_stack_HL: `EXEC_WRITE(`_SP - 1, `_H) endcase 1: case (opcode[5:4]) - `INSN_stack_AF: `EXEC_WRITE(`_SP - 1, `_F) - `INSN_stack_BC: `EXEC_WRITE(`_SP - 1, `_C) - `INSN_stack_DE: `EXEC_WRITE(`_SP - 1, `_E) - `INSN_stack_HL: `EXEC_WRITE(`_SP - 1, `_L) + `INSN_stack_AF: `EXEC_WRITE(`_SP - 2, `_F) + `INSN_stack_BC: `EXEC_WRITE(`_SP - 2, `_C) + `INSN_stack_DE: `EXEC_WRITE(`_SP - 2, `_E) + `INSN_stack_HL: `EXEC_WRITE(`_SP - 2, `_L) endcase 2: begin /* Twiddle thumbs. */ end 3: begin -- 2.39.2