From 6c1f3ad98ccd156be88c4011206605d127abee74 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 21 May 2008 23:49:17 -0400
Subject: [PATCH] Move alu_ext to its own file
---
broken-tests | 3 +--
core/GBZ80Core.v | 59 -------------------------------------------
core/insn_alu_ext.v | 61 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/broken-tests b/broken-tests
index e388d35..bae68c9 100644
--- a/broken-tests
+++ b/broken-tests
@@ -37,5 +37,4 @@ TEST 10: SP/HL instructions
E8 01 (ADD SP, 1)
E8 FF (ADD SP, -1)
F8 01 (LD HL, SP+1)
-F8 FF (LD HL, SP-1)
-
+F8 FF (LD HL, SP-1)
\ No newline at end of file
diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v
index a79b78a..b5a502c 100644
--- a/core/GBZ80Core.v
+++ b/core/GBZ80Core.v
@@ -150,65 +150,6 @@ module GBZ80Core(
`include "allinsns.v"
`undef LOCALWIRES
- wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
- wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
- wire [7:0] alu_res;
- wire [3:0] f_res;
-
- assign rlc = {tmp[6:0],tmp[7]};
- assign rlcf = {(tmp == 0 ? 1'b1 : 1'b0)
- ,2'b0,
- tmp[7]};
-
- assign rrc = {tmp[0],tmp[7:1]};
- assign rrcf = {(tmp == 0 ? 1'b1 : 1'b0),
- 2'b0,
- tmp[0]};
-
- assign rl = {tmp[6:0],`_F[4]};
- assign rlf = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
- 2'b0,
- tmp[7]};
-
- assign rr = {`_F[4],tmp[7:1]};
- assign rrf = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
- 2'b0,
- tmp[0]};
-
- assign sla = {tmp[6:0],1'b0};
- assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
- 2'b0,
- tmp[7]};
-
- assign sra = {tmp[7],tmp[7:1]};
-// assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf =
-
- assign swap = {tmp[3:0],tmp[7:4]};
- assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
- 3'b0};
-
- assign srl = {1'b0,tmp[7:1]};
- assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
- 2'b0,
- tmp[0]};
- assign sraf = srlf;
-
- /* Y U Q */
- assign {alu_res,f_res} =
- opcode[5] ? (
- opcode[4] ? (
- opcode[3] ? {srl,srlf} : {swap,swapf}
- ) : (
- opcode[3] ? {sra,sraf} : {sla,slaf}
- )
- ) : (
- opcode[4] ? (
- opcode[3] ? {rr,rrf} : {rl,rlf}
- ) : (
- opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
- )
- );
-
initial begin
`_A <= 0;
`_B <= 0;
diff --git a/core/insn_alu_ext.v b/core/insn_alu_ext.v
index b4046e8..1985586 100644
--- a/core/insn_alu_ext.v
+++ b/core/insn_alu_ext.v
@@ -1,5 +1,66 @@
`define INSN_ALU_EXT 9'b100xxxxxx
+`ifdef LOCALWIRES
+ wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
+ wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
+ wire [7:0] alu_res;
+ wire [3:0] f_res;
+
+ assign rlc = {tmp[6:0],tmp[7]};
+ assign rlcf = {(tmp == 0 ? 1'b1 : 1'b0)
+ ,2'b0,
+ tmp[7]};
+
+ assign rrc = {tmp[0],tmp[7:1]};
+ assign rrcf = {(tmp == 0 ? 1'b1 : 1'b0),
+ 2'b0,
+ tmp[0]};
+
+ assign rl = {tmp[6:0],`_F[4]};
+ assign rlf = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
+ 2'b0,
+ tmp[7]};
+
+ assign rr = {`_F[4],tmp[7:1]};
+ assign rrf = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
+ 2'b0,
+ tmp[0]};
+
+ assign sla = {tmp[6:0],1'b0};
+ assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
+ 2'b0,
+ tmp[7]};
+
+ assign sra = {tmp[7],tmp[7:1]};
+// assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf =
+
+ assign swap = {tmp[3:0],tmp[7:4]};
+ assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
+ 3'b0};
+
+ assign srl = {1'b0,tmp[7:1]};
+ assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
+ 2'b0,
+ tmp[0]};
+ assign sraf = srlf;
+
+ /* Y U Q */
+ assign {alu_res,f_res} =
+ opcode[5] ? (
+ opcode[4] ? (
+ opcode[3] ? {srl,srlf} : {swap,swapf}
+ ) : (
+ opcode[3] ? {sra,sraf} : {sla,slaf}
+ )
+ ) : (
+ opcode[4] ? (
+ opcode[3] ? {rr,rrf} : {rl,rlf}
+ ) : (
+ opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
+ )
+ );
+`endif
+
`ifdef EXECUTE
`INSN_ALU_EXT: begin
if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
--
2.43.0