From 69ca9b5f404e06ddf52dc24e40257e3f28aade3d Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sun, 30 Mar 2008 23:46:49 -0400 Subject: [PATCH] Fix part of the indentation tragedy. --- FPGABoy.ise | Bin 212301 -> 212181 bytes GBZ80Core.v | 116 ++++++++++++++++++++++++++-------------------------- 2 files changed, 58 insertions(+), 58 deletions(-) diff --git a/FPGABoy.ise b/FPGABoy.ise index 491bbb39ff44986db2211e280d815011353a3f19..50f4b037e792441108860c831baa37e5746f45e7 100644 GIT binary patch delta 7466 zcmbtZX;@R&);@b@pOb(jIFcp~Xd<8@38O*RBO(g6Qni4@p<>lqdi80s)rxhs zJz9HfTWqzZik9zQytNfAjsa^C9I2v$41$U%0&2?_NLI98@4t`dQO;g_t@mB)U3)kQ zXP-D-=x{pl>r0L!I=<4s{Ts)<{hQe96zwB+#?qefYeP>+m#D!_HAFs?_m`Qt?w{Xp zK#WRHoMD5?=<^PrC(GuO7P~-(p(}r__3~0ov3dfeJpr4sw*Owm%0_h3ri$xObJXPxhAe*?dBJ z2cO#)!`l9-il#Caf?>Cu;bH$6w@hiH-D#n0wC$Nlve+Kk@@^o)4}i1*TJi?u3{Vmd z_6#tpUY69$-mucFGYH=zg83{w9blBN5d1J!?hBI#8i@q525N~rI1-?G+|t@R1VXDh9XgAx)@(=Z~xg!>&8Q zu0bxeN`%5edX)n=La4SfAE;;X=yZD;bPh7m`W;|&H4-OSW%++P6u9b17F4_HXjvun z8EjOk`G4A~;>rU!B_bV-ghhi5idJCJ*m@cT`Gb`{Z!(E&gOzT*PFRY;mmT%FB*$8ce^=|2$BSIe@!?M4Sp5_Y>HbhH)0@DzepytPXDZ)M7%bk>ESt%XH zNgXiYsw3Tt@`Q#+dAq$Q6c5qR^ADkJh+ef)ID!+UK};?ChZX2bFVJgT6qlRXc$?gW zoP`*TCabbRIvgXeQy~`9_#;jhZ?hA}N&IQFKV8T-;`6V_Jq`7mhR43y7> zWVd880gBv$sksoO?izZ%1w7rgawnFC9TUC_529%LjK*2CwmiY>C!gbZd zMXEv6>yG>ZM18h}jlevrKjHRR8r1#6+W6h*^JFv^jpdrgGhdsXkP&nuo|R+YW??vsIUA}*oBFm>EJz3UV3jU}^oAmxi{cMaNJZS@RH)WjmR}Kg>UD~n_l0Yy zOG^kW(rf66_hFM>AGd-&#b(EkVl$EIwi{oB>6XtD{)J_j|3&Z;;G9g-Jhb2E_@|gt zlNUI98+@y)BuZR`i5bFCbS)hxNyBa~zQ|V~O|vts_12RSkms#aJorM$!in<#K%KYN z&571ySnOx~eJrPu=V#&$s(%CYJ{m>qV^WC0&EAmgqoIG+zy_ZpG6W|3>g7{~S25!9 ze#r7Q%Ke3@DBO`JaLQM&8c8aU&EqDE!lfv20cSrYc?mrHwkRGS;qg%C>OO&DKRsCj z5B-t@`*2Hf9S^@KZNSRgQ>C%^T*C<_Ea6!OZ@=f7G9braLp!!YfxlMeC>vu7Ad+>$ zHyCU#hx`7iv@I7B1GJViD=R=L_hW5XRKo|58xZ4`CfS4fFKZRv!He-!4_1%N4|YTU zQAwd4t<)XYcYqhm#r5s*Z%HQF)0eTusDkhtJ&pD#lW+lvAI*j0Q96aWKsF20cANs8 zqYS=n$Jy(s@cW^%1pD;IY$&dq>Ns`_pRXT;w9z`>^Z9JEt&_y*G}Xx7w(czdFfI&} zbkfS^*x>+5MkiaggXb76Sp^Yel+!aL_N)IbSKbc^t}P=^?P~=1TD0GdBNSQuT!rH( zd8t3-k8z>WOK@t8r7!$etmgaPLIFCN{{xb-$mz8>^xB4#T;zE|j)H-PmY)W;+-SMwOKFMyS1+{Pzg;z}mV(DP4Q>4p!p4R87}*Y-u6@X-p`eeIY@rQ~@GlFc_Eu3S9v4hc{{cM$^<+I5 z12u}88dibgUx|gZKrP9HoIs^~06!E{s@eesfk~9BgFZn<5)TnUF0|z|EDF-N|M?~V z6S`IGB;MExr*%w+DUeXe53-!DB~Ts|9eUz1`AW9hx{h2I$OhWw?#)b?s7x(6iO1rq zW;O;HZkO<{*^3+lrtwO*8PXW!tf9gd+-0YYGBw&eOCWE&UNwx~#!VCVMCypMS7q>U zyiQ$nL$Vnum+a@iM9R)!Fiwae0gy8xiI)8d_b0e0uGF#{sM+tkpwC2&qQ_0?ctpGz z0+S~i$*Yhx(Q=Y(gWQQ)G7e5n)KS?TXq%`fZ-K`o9X-Df;wS0c+fVS5Fzelgd@k1a z#D!&Ga~~-oZ<0aHeL?(@#Azkh50~JPt>_rm9!VQ_!4QniRhAn47_!gb89b}P6}(Gvqi zOmR`PH}E?#?7~i1F(u9N$*F3JK~eS*--*$Ujo>j=Z@G2jr|PKr6l6~|sz%YF*q%}G zyc=TN^nl8#w`l7HC<;y{{@@y-wERChB*teQ=Y<07pTL3=JLGhL@PAC$JBb9)i9zj!^WhD*~m>eDCL zROGw0l-c#YF%SBLYUN7)D9)BYg~_1?`rs?b3RMR75~^^~)Q+TjJU&Nl5#)7%e~ob ztbyEv`!lri)hrn+IqwRtGgqlhdCJAOz$K=lWN3qPW3$wame zOKK4yD^lx|EZvB+chqb+&Q|y1zeD*tJbC+D#=S%+k4&??(2kE%x{Vq%TXNhrh8ItpNIl-}~?MqZSb%!hMPmiO38po|Wt6;B~KTB%Br0B+T#bND~8eT`L^xFGDQFOB9z;lgpq2zlQ9ivg#|0pcMl>fNOQt{6DqOpmTX}@K3_A(m%hy9y2}-yAY%~gYdm~wZ+pwQm*o)BSbI^Z|hL&uF@pE+a@#kQg6HS{h zLh+msw+Oxo!|z^U*_i8=4g4{b{c;%S6Sc$yF^L*_yAf6;Myt=1NjBmqmnETs5#xT| z1l5V!tPE*0lD8Lg)A1;M?;;z96}4s%U-WTW%|1o->SDR=xZZh@{~Yb*SIOI0oH~+k zz^w1BB?s_gAM&llvC9YEnY)oXbb#|bElC8wd0Lf5+5^e13d|E*DESIZ^DOUd#Q^j4 zSx#IeF0U1(d^<8UhLD4JSq}M@ABh#*xWNEVF8fSn|L9a(*~{&R{zU0`Z=!s z&^~-9`qvfG?5u%CMqDTFp*fxU0r3m(qjzfoRtFeA|{#xBW6dvFuqVK4vOxITO@9YCSdnF)>HJ1As_Ta zoTJmanO_rqVl2!}F=T;#s_3Kcsm0c*4Y4G+3#}x!3vE$%7V;=wTpZWMY8yu`7dtKE zo;Z%E=!VD?GvX}hM`w{KT|x-)WGmM9YPh&7o@~Kk${}&o>=%X#@$BsGD!_+#5n~d_ zCOg+iL99=Bf!lMLm^J4G?h%&1DOfb!Cf-Z1a8F3=N!z7W0VS|HZXvqG5Xk&0WQk)1tpe6NM$26K`Y@kkociaDudsonKnoam57zP69==81>W$S(W1 zsY84@oqTJDYVz-fYVLv>x+iD}A$HdXzZ6c(AamGrLs8-P%gIscbHhq8a}6;+A1^Nq zT}!U^cy2I>y6hJn(hKQE60Uge@M__lPsnEa+%Uhec{_=G0ph2^(B0$?=|?PD@LhU@ zG$*BW>mrv>@xeMWMhwd(E7M6SSuXqzyBl!#07$wbjLgY*>V zts%~i_Spx8oA;8J=zlB4qwoJSU-!r2tUNO3FW9!7mioGQHjm86!ks2_;EviVLM=MD z2AjneW7!e)f3>_+Ch7j8iA8>!k7dXHO;gEMYgD4`v`SG}#=QkUa)}qWe^1i>CO76d zLG<27=Gdou+sJK4*dG;Q-ag_#0bx@kBn$uQaiNr}{j0@tCjG4_(RDwGw3A@Vk>sxU z(SDnRT~IH!y!8LH{CQKai0S!c>VIqZ`NHe@q&%#o~eFH>;g62vB zeEh{53i>_`@DbCU=~`wn_=%0qbfwiPr6*0d+A4a|-CbU5deJSG--V97Em4*!KmY9Q TeQDwLzLNZ5LeV&hCE@=Cms!@8 delta 7516 zcma)B3s_Xu_CNc~K4(T?2A?y|pn@|zRAh#i3Ns=qDgr9PXuOoMuryK8Eb)JMjXU16?7177O>@{hS-Sq9Vbb3GBvY6HoJ zHEL79T`pI)xI;{s683G`BAd<_E4?Ypw2g1P&jq4wsT15$r?TgRAXcLyzrrkymaT|^ zjp82{737JsW;mfSkSEZhi46M(Hv~a$hR~%rzVR)qkiBUG_b=lQ$X43M)-Y)ujvw8C zATUzf>DwPehkBOv(?v=gP0Ytd1klsf}njoi-iY$S>eN5`h zk{a0(8_fzM|0N<=$HJ37CV4#{gtqdpAfm5{EQhSVIc3|^It6GDFj`b&lWWRcKos!@MtB$iRJVcXc^gBwJ>KQD35Rhldhy*O}#|oB>;;)EBaJDzX~{ zosQ(g_qs^+KK>TE|A!NQ5nX6r3vQkU(h4!2I#LK3o{QP@W~lZwveqEbc^O&W4J=+3 zau^D|#<5ldNWHae*&Oio*2&k>bgUR(2`SzN^#!gQ0$=o{FJO;Id|{WjPTjyPmMyor zugTy7Fz45oLYcRYybBVaNKy+iKB?Z9hI6eLO9Nr^Wh-oEF?n1w${Y8?86PEU9R<}s z#z3hLzZc`PM$wg+zLu+GE_Q?RWBv_H@vq)s9uTh}8fwHeN+v-50DYDO9V4;xXKea2jZr6Y@Db3eU>WRrG6nl9-DV zn6sj%Fk|2(atQJUDiya~=|)65dlE_pT1X`X4T>ZyVELeNY~uhZ8nl|d?+cN>k)#xI ze3hCjz4)Ez*r|n_59YXOG!%+TUxIY7$ty>)727DIh+B^}~&jg0XqIOT(e482B3Wit<_fbNOkKIt`OZV`JMmP5r!YZOMr37kmjQN&Jykk`qZ!o zT>XuKl?f6Rc45kV{urtje>?Vi%~vzA)Sp`kd9}6LwQ^Ve;$eNpM#>IdWF?j_5!-?^aHdF zH3mK!PG83iZ-|y9;j*)wdSc&HoTlYCE*l8x!}NhAK6I14l0-g|)yh`cc2;l<6N65= zY?mcF;GDra%pz_F-w++S1F<2hs49u$>R;*31tG!pTJi*Y7? zIbN~_kBkftnL7r;Lr*r9;(1$tn6+0Z^F7w5XQZ0j`;p5noZ-8@{fjkCN zm{xIX8a;=}zg!IIVLEafa>7*dt(+&ibfX*Oho!Q_0zF2U$Qg(op=6s!!mJTm?>05} z1FD_xLHw~4E-R=WT_8V0-U#t@jewF7@zKZUlh0*KZGGgPChO}+_Xe7Qj>_JX9LHlZ zvx$ZvLsbO#sw2olkP)u(`bBC+&dO!{X53}J<;ye<f{lZ{eny`dI3OR##R* zbGTk}D^aouDd!#JK10g3qhK0oCI=vAWGef|Vz@I>sko9#Z(z=@tDwgyt->Wq8jgrJ z3n5~ZiCl-QQQ}GB1iMD*$Tx6el%DPK610pmkcZ$iTF;hvLBeRgcWW3o8ol0K!0p2L z9&e`evAFkhAa}G;Lwb{7Byo9z>4hzL^boX-R;dp%H5kF7S=@c}uyG?8A`IjUutccj zr}(KD+0)UmCSshob%;cY^+*b&6L7hFFXxBjn?-OZLZvRFu?SjD`BL<*S_bZ84CHHw z9ivpVzQ}DyvkN_7(U^4clT+Ckqv8)2t_`gl(!gh|LA-Sn#_CyXIAo7CsSmQASe~H? zoEKu;+zD65ma`8hLg6?I*$?iKD)INQNOQmg#t##4a3mdv*ey$F9v%)kzi{j9Ktx&$ z-$$Cr2hb8}WG_cT(0HA^jgCjN@)M9YUaz_BFWH8tc1Av@MK^AkA$PoiEQ71#4PM8Y z!;bf-F#bm@N%3Jm7AskJ5e!jA_SOrK9;Ib#G9V{Pudxo4-b3ZqVbt;B^&kZUFxP}Y^=^SBl`+*b_K%(ZD4CClZ8p+3%NuztlmT?IchMD10=c-1ZyT($S?u|c{tKt-(9TjIn{#k*zr9O+pkdMM=_HK>UN-^qG!=Pu+O%zmFq{1H^O{vTa| zA>CUES(9}E7p3cPweCGS5LYYS;l9H3weI2^ZyC2spk#8o_(B^Vr}FxoIKGaUG=!1K z{$V?bi;wVUF|^0NusqHnez}nwrz4l(Oq}>08w;xVaqRg;V2M|$uSo#6>VjnM8J4eM zG~~o<6~Fb9R-k*2-hsk+i+JFH1Q4_$s1PiNxzfeIFxb?Ohv76k8W z;BVk+*;kNfRz)3`#v^v+o6KrQN3G%FF!Y){rWijCISrKFM*Y@s&INmkiv`yy7Lo%Q zQ!HV?7okq^LCFLB>LhEKG#ll0TP1r?zOa#2;Cp&$B{)xAJfb;`oWa`p1o7Ljd7Sf^ zbbJ*V+CV*!-sKt1$E;mg0)iBq677Z5@Bjwll7Ifr75%?zQ)MsfZVpe%jKXkdW5oRUn#7b^V z(y~_#ke6f-zaA<}Qh5O#hKZ|UNE&X#UZ?nd2yKl7w`46_EQ9c5J=>y$jO2Ls?j$Hm zj`TXgHK6(JIGT;VZeGLvglWH21cnqHsRnb3maR&I%#?V|sVK=h{Nyq(nm3`{k2|3v zMVD12Z9?)^6BC6;>G}(F07mqniUgvL%ToFgX0N)K`4Ib^6Sy5HKNn9{VQ`wsT&=_F zW^xEG_WoZ=oZ5BZ?P=>+r-k4;T}MhFXu3{4Lh6iUS5{JAEFslE#&q$W%>*#rkhPYX zjP13kn0tf_^@Zf0cv<%Uk{gT>+)Si^C-SDJTomfp{EPS@nadic2S#5sh24R@AKinC zcIX?}?Dky;qf&!eJ{2-kE#xb>n5t*5y$n)|DQpSnxI1cpp@)$F)DdPFVt-c0-9^0m z>C_E-=<4f`Wl?G#Phhqc5AKP z?{sy{V>*~$6#~p6bAy?rIhJlu>sXp?TUs-PjAN6&6RcA@(P&_qFng-VYDc31bwZms zM+h1a)d8_sm_JoSKlTC{)9w(TK;Fgp{()| z%t>UUgNuJzs7ZQ`o3jd8$72uX84VbHWr2+6&- zg`dPZx-YrAuLI&!!GD?vv3j}<;?#8Vu>+#4OjwZm97NezL27w!Ub>}VhlONzVN*5; zs#nRUPAMC09iUt!{PZf>-WBJ)DjCLuk=zrGrW2izGlwj2sP-B!bV(455y)B)Ah4&}Lb#5_VAs;b`##?L3ov{UeF!T#6CF=?k@g|K)TIn_B| zRuH|MTygFcWD5H1=M`QrVAqjJicW=v1<4C!NenHcRWb$(mMFr8jNgYwMVlFuG z>DHc;$fgwAcdgXeD4g9%LWG!IMA@||>6`XdhTGYP_asMIVcS>4qfb)4O*lA$DQq7_ zHlf6KlW;bZ_zQirh>N`|jDj4Pymu|{-Z7~pgkyY6RbN7+nY+s2eZV$8_;BUd2 zX8jKl-JM4U3t6ubU1w4^2%21y{9ln1h4r~)LY94ZN=mmd$3*_;awTT3)-JJ~4^-SW zHGh$an?Ta>-xV>#b{%n7|3}Ux@BYP#s>8&2cRq+*OTSy3J;LU!uAZ}<~SX%?+^wYB+36@ zy^Rn4$9hYJM+g6Fy;m2!l1Cmz%H2ZJo)(DbXZthE{%_6h1v^@Zhmr<`1_ud0%h_F$ zpwOYhYz4c44GIB=>n2*!;NSrN UY>%F7fk#hC-T;1BSbLlO8!Zdx_y7O^ diff --git a/GBZ80Core.v b/GBZ80Core.v index c0c2b26..338c2d7 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -146,7 +146,7 @@ module GBZ80Core( `EXEC_NEXTADDR_PCINC; rd <= 1; end - 1: begin + 1: begin `EXEC_INC_PC; if (opcode[5:3] == `INSN_reg_dHL) begin address <= {registers[`REG_H], registers[`REG_L]}; @@ -157,7 +157,7 @@ module GBZ80Core( `EXEC_NEWCYCLE; end end - 2: begin + 2: begin `EXEC_NEWCYCLE; end endcase @@ -170,13 +170,13 @@ module GBZ80Core( case (cycle) 0: begin case (opcode[2:0]) - `INSN_reg_A: begin wdata <= registers[`REG_A]; end - `INSN_reg_B: begin wdata <= registers[`REG_B]; end - `INSN_reg_C: begin wdata <= registers[`REG_C]; end - `INSN_reg_D: begin wdata <= registers[`REG_D]; end - `INSN_reg_E: begin wdata <= registers[`REG_E]; end - `INSN_reg_H: begin wdata <= registers[`REG_H]; end - `INSN_reg_L: begin wdata <= registers[`REG_L]; end + `INSN_reg_A: wdata <= registers[`REG_A]; + `INSN_reg_B: wdata <= registers[`REG_B]; + `INSN_reg_C: wdata <= registers[`REG_C]; + `INSN_reg_D: wdata <= registers[`REG_D]; + `INSN_reg_E: wdata <= registers[`REG_E]; + `INSN_reg_H: wdata <= registers[`REG_H]; + `INSN_reg_L: wdata <= registers[`REG_L]; endcase address <= {registers[`REG_H], registers[`REG_L]}; wr <= 1; rd <= 0; @@ -189,11 +189,11 @@ module GBZ80Core( end `INSN_LD_reg_HL: begin case(cycle) - 0: begin + 0: begin address <= {registers[`REG_H], registers[`REG_L]}; rd <= 1; end - 1: begin + 1: begin tmp <= rdata; `EXEC_INC_PC; `EXEC_NEWCYCLE; @@ -204,13 +204,13 @@ module GBZ80Core( `EXEC_INC_PC; `EXEC_NEWCYCLE; case (opcode[2:0]) - `INSN_reg_A: begin tmp <= registers[`REG_A]; end - `INSN_reg_B: begin tmp <= registers[`REG_B]; end - `INSN_reg_C: begin tmp <= registers[`REG_C]; end - `INSN_reg_D: begin tmp <= registers[`REG_D]; end - `INSN_reg_E: begin tmp <= registers[`REG_E]; end - `INSN_reg_H: begin tmp <= registers[`REG_H]; end - `INSN_reg_L: begin tmp <= registers[`REG_L]; end + `INSN_reg_A: tmp <= registers[`REG_A]; + `INSN_reg_B: tmp <= registers[`REG_B]; + `INSN_reg_C: tmp <= registers[`REG_C]; + `INSN_reg_D: tmp <= registers[`REG_D]; + `INSN_reg_E: tmp <= registers[`REG_E]; + `INSN_reg_H: tmp <= registers[`REG_H]; + `INSN_reg_L: tmp <= registers[`REG_L]; endcase end `INSN_LD_reg_imm16: begin @@ -241,7 +241,7 @@ module GBZ80Core( end `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */ case (cycle) - 0: begin + 0: begin wr <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; case (opcode[5:4]) @@ -251,7 +251,7 @@ module GBZ80Core( `INSN_stack_HL: wdata <= registers[`REG_H]; endcase end - 1: begin + 1: begin wr <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; case (opcode[5:4]) @@ -262,7 +262,7 @@ module GBZ80Core( endcase end 2: begin /* TWIDDLE OUR FUCKING THUMBS! */ end - 3: begin + 3: begin `EXEC_NEWCYCLE; `EXEC_INC_PC; end @@ -270,15 +270,15 @@ module GBZ80Core( end `INSN_POP_reg: begin /* POP is 12 cycles! */ case (cycle) - 0: begin + 0: begin rd <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}; end - 1: begin + 1: begin rd <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}; end - 2: begin + 2: begin `EXEC_NEWCYCLE; `EXEC_INC_PC; end @@ -295,7 +295,7 @@ module GBZ80Core( wdata <= registers[`REG_A]; end end - 1: begin + 1: begin `EXEC_NEWCYCLE; `EXEC_INC_PC; end @@ -303,7 +303,7 @@ module GBZ80Core( end `INSN_LDx_AHL: begin case (cycle) - 0: begin + 0: begin address <= {registers[`REG_H],registers[`REG_L]}; if (opcode[3]) begin // LDx A, (HL) rd <= 1; @@ -327,14 +327,14 @@ module GBZ80Core( `EXEC_NEWCYCLE; `EXEC_INC_PC; case (opcode[2:0]) - `INSN_reg_A: begin tmp <= registers[`REG_A]; end - `INSN_reg_B: begin tmp <= registers[`REG_B]; end - `INSN_reg_C: begin tmp <= registers[`REG_C]; end - `INSN_reg_D: begin tmp <= registers[`REG_D]; end - `INSN_reg_E: begin tmp <= registers[`REG_E]; end - `INSN_reg_H: begin tmp <= registers[`REG_H]; end - `INSN_reg_L: begin tmp <= registers[`REG_L]; end - `INSN_reg_dHL: begin tmp <= rdata; end + `INSN_reg_A: tmp <= registers[`REG_A]; + `INSN_reg_B: tmp <= registers[`REG_B]; + `INSN_reg_C: tmp <= registers[`REG_C]; + `INSN_reg_D: tmp <= registers[`REG_D]; + `INSN_reg_E: tmp <= registers[`REG_E]; + `INSN_reg_H: tmp <= registers[`REG_H]; + `INSN_reg_L: tmp <= registers[`REG_L]; + `INSN_reg_dHL: tmp <= rdata; endcase end end @@ -345,19 +345,19 @@ module GBZ80Core( `INSN_RST: begin case (cycle) 0: begin - `EXEC_INC_PC; // This goes FIRST + `EXEC_INC_PC; // This goes FIRST in RST end - 1: begin + 1: begin wr <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; wdata <= registers[`REG_PCH]; end - 2: begin + 2: begin wr <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}-2; wdata <= registers[`REG_PCL]; end - 3: begin + 3: begin `EXEC_NEWCYCLE; {registers[`REG_PCH],registers[`REG_PCL]} <= {10'b0,opcode[5:3],3'b0}; @@ -390,8 +390,8 @@ module GBZ80Core( casex (opcode) `INSN_LD_reg_imm8: case (cycle) - 0: cycle <= 1; - 1: case (opcode[5:3]) + 0: cycle <= 1; + 1: case (opcode[5:3]) `INSN_reg_A: begin registers[`REG_A] <= rdata; cycle <= 0; end `INSN_reg_B: begin registers[`REG_B] <= rdata; cycle <= 0; end `INSN_reg_C: begin registers[`REG_C] <= rdata; cycle <= 0; end @@ -401,7 +401,7 @@ module GBZ80Core( `INSN_reg_L: begin registers[`REG_L] <= rdata; cycle <= 0; end `INSN_reg_dHL: cycle <= 2; endcase - 2: cycle <= 0; + 2: cycle <= 0; endcase `INSN_HALT: begin /* Nothing needs happen here. */ @@ -409,8 +409,8 @@ module GBZ80Core( end `INSN_LD_HL_reg: begin case (cycle) - 0: cycle <= 1; - 1: cycle <= 0; + 0: cycle <= 1; + 1: cycle <= 0; endcase end `INSN_LD_reg_HL: begin @@ -418,13 +418,13 @@ module GBZ80Core( 0: cycle <= 1; 1: begin case (opcode[5:3]) - `INSN_reg_A: begin registers[`REG_A] <= tmp; end - `INSN_reg_B: begin registers[`REG_B] <= tmp; end - `INSN_reg_C: begin registers[`REG_C] <= tmp; end - `INSN_reg_D: begin registers[`REG_D] <= tmp; end - `INSN_reg_E: begin registers[`REG_E] <= tmp; end - `INSN_reg_H: begin registers[`REG_H] <= tmp; end - `INSN_reg_L: begin registers[`REG_L] <= tmp; end + `INSN_reg_A: registers[`REG_A] <= tmp; + `INSN_reg_B: registers[`REG_B] <= tmp; + `INSN_reg_C: registers[`REG_C] <= tmp; + `INSN_reg_D: registers[`REG_D] <= tmp; + `INSN_reg_E: registers[`REG_E] <= tmp; + `INSN_reg_H: registers[`REG_H] <= tmp; + `INSN_reg_L: registers[`REG_L] <= tmp; endcase cycle <= 0; end @@ -432,13 +432,13 @@ module GBZ80Core( end `INSN_LD_reg_reg: begin case (opcode[5:3]) - `INSN_reg_A: begin registers[`REG_A] <= tmp; end - `INSN_reg_B: begin registers[`REG_B] <= tmp; end - `INSN_reg_C: begin registers[`REG_C] <= tmp; end - `INSN_reg_D: begin registers[`REG_D] <= tmp; end - `INSN_reg_E: begin registers[`REG_E] <= tmp; end - `INSN_reg_H: begin registers[`REG_H] <= tmp; end - `INSN_reg_L: begin registers[`REG_L] <= tmp; end + `INSN_reg_A: registers[`REG_A] <= tmp; + `INSN_reg_B: registers[`REG_B] <= tmp; + `INSN_reg_C: registers[`REG_C] <= tmp; + `INSN_reg_D: registers[`REG_D] <= tmp; + `INSN_reg_E: registers[`REG_E] <= tmp; + `INSN_reg_H: registers[`REG_H] <= tmp; + `INSN_reg_L: registers[`REG_L] <= tmp; endcase end `INSN_LD_reg_imm16: begin @@ -610,7 +610,7 @@ module GBZ80Core( case (cycle) 0: cycle <= 1; 1: cycle <= 2; - 2: cycle <= 3; + 2: cycle <= 3; 3: begin cycle <= 0; {registers[`REG_SPH],registers[`REG_SPL]} <= -- 2.43.0