From 5c33c5c001049403ac33d71bfbe0115c318c1b4c Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sun, 6 Apr 2008 04:36:51 -0400 Subject: [PATCH] Rework it all to use the new macros. --- GBZ80Core.v | 27 ++++------------------ insn_alu8.v | 6 ++--- insn_alu_a.v | 28 +++++++++++------------ insn_call-callcc.v | 45 +++++++++++++----------------------- insn_di-ei.v | 4 ++-- insn_halt.v | 2 +- insn_incdec16.v | 56 ++++++++++++--------------------------------- insn_jp-jpcc.v | 27 +++++++++------------- insn_jp_hl.v | 9 ++------ insn_jr-jrcc.v | 25 ++++++++------------ insn_ld_hl_reg.v | 20 ++++++++-------- insn_ld_reg_hl.v | 30 ++++++++++-------------- insn_ld_reg_imm16.v | 30 ++++++++++-------------- insn_ld_reg_imm8.v | 37 ++++++++++++------------------ insn_ld_reg_reg.v | 32 +++++++++++++------------- insn_ld_sp_hl.v | 14 +++++------- insn_ldh_ac.v | 20 ++++++---------- insn_ldx_ahl.v | 26 ++++++++------------- insn_nop.v | 4 ++-- insn_pop_reg.v | 33 +++++++++++--------------- insn_push_reg.v | 39 ++++++++++++------------------- insn_ret-retcc.v | 35 ++++++++++------------------ insn_rst.v | 24 +++++-------------- insn_vop_intr.v | 6 ++--- 24 files changed, 217 insertions(+), 362 deletions(-) diff --git a/GBZ80Core.v b/GBZ80Core.v index 6039b30..f438339 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -107,19 +107,11 @@ `define INSN_alu_SCF 3'b110 `define INSN_alu_CCF 3'b111 -`define EXEC_INC_PC \ - `_PC <= `_PC + 1 -`define EXEC_NEXTADDR_PCINC \ - address <= `_PC + 1 -`define EXEC_NEWCYCLE \ - begin newcycle <= 1; rd <= 1; wr <= 0; end -`define EXEC_WRITE(ad, da) \ - begin address <= (ad); \ - wdata <= (da); \ - wr <= 1; end -`define EXEC_READ(ad) \ - begin address <= (ad); \ - rd <= 1; end +`define EXEC_INC_PC `_PC <= `_PC + 1; +`define EXEC_NEXTADDR_PCINC address <= `_PC + 1; +`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end +`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end +`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end module GBZ80Core( input clk, @@ -217,19 +209,10 @@ module GBZ80Core( state <= `STATE_EXECUTE; end `STATE_EXECUTE: begin - casex (opcode) `define EXECUTE `include "allinsns.v" `undef EXECUTE - `INSN_DI: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; - end - `INSN_EI: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; - end default: $stop; endcase diff --git a/insn_alu8.v b/insn_alu8.v index 6abcb90..161418b 100644 --- a/insn_alu8.v +++ b/insn_alu8.v @@ -1,10 +1,10 @@ `ifdef EXECUTE `INSN_ALU8: begin if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) - `EXEC_READ(_HL); + `EXEC_READ(`_HL) else begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC case (opcode[2:0]) `INSN_reg_A: tmp <= `_A; `INSN_reg_B: tmp <= `_B; diff --git a/insn_alu_a.v b/insn_alu_a.v index fe3315a..57a74fc 100644 --- a/insn_alu_a.v +++ b/insn_alu_a.v @@ -1,7 +1,7 @@ `ifdef EXECUTE `INSN_ALU_A: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC end `endif @@ -9,30 +9,30 @@ `INSN_ALU_A: begin case(opcode[5:3]) `INSN_alu_RLCA: begin - registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]}; - registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]}; + `_A <= {`_A[6:0],`_A[7]}; + `_F <= {`_F[7:5],`_A[7],`_F[3:0]}; end `INSN_alu_RRCA: begin - registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]}; - registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]}; + `_A <= {`_A[0],`_A[7:1]}; + `_F <= {`_F[7:5],`_A[0],`_F[3:0]}; end `INSN_alu_RLA: begin - registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]}; - registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]}; + `_A <= {`_A[6:0],`_F[4]}; + `_F <= {`_F[7:5],`_A[7],`_F[3:0]}; end `INSN_alu_RRA: begin - registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]}; - registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]}; + `_A <= {`_A[4],`_A[7:1]}; + `_F <= {`_F[7:5],`_A[0],`_F[3:0]}; end `INSN_alu_CPL: begin - registers[`REG_A] <= ~registers[`REG_A]; - registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]}; + `_A <= ~`_A; + `_F <= {`_F[7],1'b1,1'b1,`_F[4:0]}; end `INSN_alu_SCF: begin - registers[`REG_F] <= {registers[`REG_F][7:5],1'b1,registers[`REG_F][3:0]}; + `_F <= {`_F[7:5],1'b1,`_F[3:0]}; end `INSN_alu_CCF: begin - registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]}; + `_F <= {`_F[7:5],~`_F[4],`_F[3:0]}; end endcase end diff --git a/insn_call-callcc.v b/insn_call-callcc.v index bb7c14a..a446a3d 100644 --- a/insn_call-callcc.v +++ b/insn_call-callcc.v @@ -2,39 +2,27 @@ `INSN_CALL,`INSN_CALLCC: begin case (cycle) 0: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; + `EXEC_INC_PC + `EXEC_READ(`_PC + 1) end 1: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; + `EXEC_INC_PC + `EXEC_READ(`_PC + 1) end 2: begin - `EXEC_INC_PC; + `EXEC_INC_PC if (!opcode[0]) // i.e., is callcc /* We need to check the condition code to bail out. */ case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NZ: if (`_F[7]) `EXEC_NEWCYCLE + `INSN_cc_Z: if (~`_F[7]) `EXEC_NEWCYCLE + `INSN_cc_NC: if (`_F[4]) `EXEC_NEWCYCLE + `INSN_cc_C: if (~`_F[4]) `EXEC_NEWCYCLE endcase end - 3: begin - address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; - wdata <= registers[`REG_PCH]; - wr <= 1; - end - 4: begin - address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; - wdata <= registers[`REG_PCL]; - wr <= 1; - end - 5: begin - `EXEC_NEWCYCLE; /* do NOT increment the PC */ - end + 3: `EXEC_WRITE(`_SP - 1, `_PCH) + 4: `EXEC_WRITE(`_SP - 2, `_PCL) + 5: `EXEC_NEWCYCLE endcase end `endif @@ -46,11 +34,10 @@ 1: tmp <= rdata; // tmp contains newpcl 2: tmp2 <= rdata; // tmp2 contains newpch 3: begin /* type F */ end - 4: registers[`REG_PCH] <= tmp2; - 5: begin - {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]} - 2; - registers[`REG_PCL] <= tmp; + 4: `_PCH <= tmp2; + 5: begin + `_PCL <= tmp; + `_SP <= `_SP - 2; end endcase end diff --git a/insn_di-ei.v b/insn_di-ei.v index 3b06578..eff1de2 100644 --- a/insn_di-ei.v +++ b/insn_di-ei.v @@ -1,7 +1,7 @@ `ifdef EXECUTE `INSN_DI,`INSN_EI: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC end `endif diff --git a/insn_halt.v b/insn_halt.v index 20340f8..4d2573f 100644 --- a/insn_halt.v +++ b/insn_halt.v @@ -1,6 +1,6 @@ `ifdef EXECUTE `INSN_HALT: begin - `EXEC_NEWCYCLE; + `EXEC_NEWCYCLE /* XXX Interrupts needed for HALT. */ end `endif diff --git a/insn_incdec16.v b/insn_incdec16.v index 01f919c..95e0d38 100644 --- a/insn_incdec16.v +++ b/insn_incdec16.v @@ -1,29 +1,15 @@ `ifdef EXECUTE `INSN_INCDEC16: begin case (cycle) - 0: begin - case (opcode[5:4]) - `INSN_reg16_BC: begin - tmp <= registers[`REG_B]; - tmp2 <= registers[`REG_C]; - end - `INSN_reg16_DE: begin - tmp <= registers[`REG_D]; - tmp2 <= registers[`REG_E]; - end - `INSN_reg16_HL: begin - tmp <= registers[`REG_H]; - tmp2 <= registers[`REG_L]; - end - `INSN_reg16_SP: begin - tmp <= registers[`REG_SPH]; - tmp2 <= registers[`REG_SPL]; - end - endcase - end + 0: case (opcode[5:4]) + `INSN_reg16_BC: {tmp,tmp2} <= `_BC; + `INSN_reg16_DE: {tmp,tmp2} <= `_DE; + `INSN_reg16_HL: {tmp,tmp2} <= `_HL; + `INSN_reg16_SP: {tmp,tmp2} <= `_SP; + endcase 1: begin - `EXEC_INC_PC; - `EXEC_NEWCYCLE; + `EXEC_INC_PC + `EXEC_NEWCYCLE end endcase end @@ -34,26 +20,12 @@ case (cycle) 0: {tmp,tmp2} <= {tmp,tmp2} + (opcode[3] ? 16'hFFFF : 16'h0001); - 1: begin - case (opcode[5:4]) - `INSN_reg16_BC: begin - registers[`REG_B] <= tmp; - registers[`REG_C] <= tmp2; - end - `INSN_reg16_DE: begin - registers[`REG_D] <= tmp; - registers[`REG_E] <= tmp2; - end - `INSN_reg16_HL: begin - registers[`REG_H] <= tmp; - registers[`REG_L] <= tmp2; - end - `INSN_reg16_SP: begin - registers[`REG_SPH] <= tmp; - registers[`REG_SPL] <= tmp2; - end - endcase - end + 1: case (opcode[5:4]) + `INSN_reg16_BC: `_BC <= {tmp,tmp2}; + `INSN_reg16_DE: `_DE <= {tmp,tmp2}; + `INSN_reg16_HL: `_HL <= {tmp,tmp2}; + `INSN_reg16_SP: `_SP <= {tmp,tmp2}; + endcase endcase end `endif diff --git a/insn_jp-jpcc.v b/insn_jp-jpcc.v index 2b2e52b..7c8fb22 100644 --- a/insn_jp-jpcc.v +++ b/insn_jp-jpcc.v @@ -2,30 +2,26 @@ `INSN_JP_imm,`INSN_JPCC_imm: begin case (cycle) 0: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; + `EXEC_INC_PC + `EXEC_READ(`_PC + 1) end 1: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; + `EXEC_INC_PC + `EXEC_READ(`_PC + 1) end 2: begin - `EXEC_INC_PC; + `EXEC_INC_PC if (!opcode[0]) begin // i.e., JP cc,nn /* We need to check the condition code to bail out. */ case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NZ: if (`_F[7]) `EXEC_NEWCYCLE + `INSN_cc_Z: if (~`_F[7]) `EXEC_NEWCYCLE + `INSN_cc_NC: if (`_F[4]) `EXEC_NEWCYCLE + `INSN_cc_C: if (~`_F[4]) `EXEC_NEWCYCLE endcase end end - 3: begin - `EXEC_NEWCYCLE; - end + 3: `EXEC_NEWCYCLE endcase end `endif @@ -36,8 +32,7 @@ 0: begin /* type F */ end 1: tmp <= rdata; // tmp contains newpcl 2: tmp2 <= rdata; // tmp2 contains newpch - 3: {registers[`REG_PCH],registers[`REG_PCL]} <= - {tmp2,tmp}; + 3: `_PC <= {tmp2,tmp}; endcase end `endif diff --git a/insn_jp_hl.v b/insn_jp_hl.v index 4ee380a..4aa9a41 100644 --- a/insn_jp_hl.v +++ b/insn_jp_hl.v @@ -1,12 +1,7 @@ `ifdef EXECUTE - `INSN_JP_HL: begin - `EXEC_NEWCYCLE; - end + `INSN_JP_HL: `EXEC_NEWCYCLE `endif `ifdef WRITEBACK - `INSN_JP_HL: begin - {registers[`REG_PCH],registers[`REG_PCL]} <= - {registers[`REG_H],registers[`REG_L]}; - end + `INSN_JP_HL: `_PC <= `_HL; `endif diff --git a/insn_jr-jrcc.v b/insn_jr-jrcc.v index 7a869b3..767db6a 100644 --- a/insn_jr-jrcc.v +++ b/insn_jr-jrcc.v @@ -2,25 +2,22 @@ `INSN_JR_imm,`INSN_JRCC_imm: begin case (cycle) 0: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; + `EXEC_INC_PC + `EXEC_READ(`_PC + 1) end - 1: begin - `EXEC_INC_PC; + 1: begin + `EXEC_INC_PC if (opcode[5]) begin // i.e., JP cc,nn /* We need to check the condition code to bail out. */ case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NZ: if (`_F[7]) `EXEC_NEWCYCLE + `INSN_cc_Z: if (~`_F[7]) `EXEC_NEWCYCLE + `INSN_cc_NC: if (`_F[4]) `EXEC_NEWCYCLE + `INSN_cc_C: if (~`_F[4]) `EXEC_NEWCYCLE endcase end end - 2: begin - `EXEC_NEWCYCLE; - end + 2: `EXEC_NEWCYCLE endcase end `endif @@ -30,9 +27,7 @@ case (cycle) 0: begin /* type F */ end 1: tmp <= rdata; - 2: {registers[`REG_PCH],registers[`REG_PCL]} <= - {registers[`REG_PCH],registers[`REG_PCL]} + - {tmp[7]?8'hFF:8'h00,tmp}; + 2: `_PC <= `_PC + {tmp[7]?8'hFF:8'h00,tmp}; endcase end `endif diff --git a/insn_ld_hl_reg.v b/insn_ld_hl_reg.v index 0b98431..fdf3d9b 100644 --- a/insn_ld_hl_reg.v +++ b/insn_ld_hl_reg.v @@ -3,20 +3,20 @@ case (cycle) 0: begin case (opcode[2:0]) - `INSN_reg_A: wdata <= registers[`REG_A]; - `INSN_reg_B: wdata <= registers[`REG_B]; - `INSN_reg_C: wdata <= registers[`REG_C]; - `INSN_reg_D: wdata <= registers[`REG_D]; - `INSN_reg_E: wdata <= registers[`REG_E]; - `INSN_reg_H: wdata <= registers[`REG_H]; - `INSN_reg_L: wdata <= registers[`REG_L]; + `INSN_reg_A: wdata <= `_A; + `INSN_reg_B: wdata <= `_B; + `INSN_reg_C: wdata <= `_C; + `INSN_reg_D: wdata <= `_D; + `INSN_reg_E: wdata <= `_E; + `INSN_reg_H: wdata <= `_H; + `INSN_reg_L: wdata <= `_L; endcase - address <= {registers[`REG_H], registers[`REG_L]}; + address <= `_HL; wr <= 1; rd <= 0; end 1: begin - `EXEC_INC_PC; - `EXEC_NEWCYCLE; + `EXEC_INC_PC + `EXEC_NEWCYCLE end endcase end diff --git a/insn_ld_reg_hl.v b/insn_ld_reg_hl.v index 3fc7862..e420f2f 100644 --- a/insn_ld_reg_hl.v +++ b/insn_ld_reg_hl.v @@ -1,14 +1,10 @@ `ifdef EXECUTE `INSN_LD_reg_HL: begin case(cycle) - 0: begin - address <= {registers[`REG_H], registers[`REG_L]}; - rd <= 1; - end + 0: `EXEC_READ(`_HL) 1: begin - tmp <= rdata; - `EXEC_INC_PC; - `EXEC_NEWCYCLE; + `EXEC_INC_PC + `EXEC_NEWCYCLE end endcase end @@ -18,17 +14,15 @@ `INSN_LD_reg_HL: begin case (cycle) 0: begin end - 1: begin - case (opcode[5:3]) - `INSN_reg_A: registers[`REG_A] <= tmp; - `INSN_reg_B: registers[`REG_B] <= tmp; - `INSN_reg_C: registers[`REG_C] <= tmp; - `INSN_reg_D: registers[`REG_D] <= tmp; - `INSN_reg_E: registers[`REG_E] <= tmp; - `INSN_reg_H: registers[`REG_H] <= tmp; - `INSN_reg_L: registers[`REG_L] <= tmp; - endcase - end + 1: case (opcode[5:3]) + `INSN_reg_A: `_A <= rdata; + `INSN_reg_B: `_B <= rdata; + `INSN_reg_C: `_C <= rdata; + `INSN_reg_D: `_D <= rdata; + `INSN_reg_E: `_E <= rdata; + `INSN_reg_H: `_H <= rdata; + `INSN_reg_L: `_L <= rdata; + endcase endcase end `endif diff --git a/insn_ld_reg_imm16.v b/insn_ld_reg_imm16.v index b9bd84e..cf79aaa 100644 --- a/insn_ld_reg_imm16.v +++ b/insn_ld_reg_imm16.v @@ -1,16 +1,10 @@ `ifdef EXECUTE `INSN_LD_reg_imm16: begin - `EXEC_INC_PC; + `EXEC_INC_PC case (cycle) - 0: begin - `EXEC_NEXTADDR_PCINC; - rd <= 1; - end - 1: begin - `EXEC_NEXTADDR_PCINC; - rd <= 1; - end - 2: begin `EXEC_NEWCYCLE; end + 0: `EXEC_READ(`_PC + 1) + 1: `EXEC_READ(`_PC + 1) + 2: `EXEC_NEWCYCLE endcase end `endif @@ -21,18 +15,18 @@ 0: begin /* */ end 1: begin case (opcode[5:4]) - `INSN_reg16_BC: registers[`REG_C] <= rdata; - `INSN_reg16_DE: registers[`REG_E] <= rdata; - `INSN_reg16_HL: registers[`REG_L] <= rdata; - `INSN_reg16_SP: registers[`REG_SPL] <= rdata; + `INSN_reg16_BC: `_C <= rdata; + `INSN_reg16_DE: `_E <= rdata; + `INSN_reg16_HL: `_L <= rdata; + `INSN_reg16_SP: `_SPL <= rdata; endcase end 2: begin case (opcode[5:4]) - `INSN_reg16_BC: registers[`REG_B] <= rdata; - `INSN_reg16_DE: registers[`REG_D] <= rdata; - `INSN_reg16_HL: registers[`REG_H] <= rdata; - `INSN_reg16_SP: registers[`REG_SPH] <= rdata; + `INSN_reg16_BC: `_B <= rdata; + `INSN_reg16_DE: `_D <= rdata; + `INSN_reg16_HL: `_H <= rdata; + `INSN_reg16_SP: `_SPH <= rdata; endcase end endcase diff --git a/insn_ld_reg_imm8.v b/insn_ld_reg_imm8.v index 77768e0..7340421 100644 --- a/insn_ld_reg_imm8.v +++ b/insn_ld_reg_imm8.v @@ -2,24 +2,17 @@ `INSN_LD_reg_imm8: begin case (cycle) 0: begin - `EXEC_INC_PC; - `EXEC_NEXTADDR_PCINC; - rd <= 1; + `EXEC_INC_PC + `EXEC_READ(`_PC + 1) end 1: begin - `EXEC_INC_PC; - if (opcode[5:3] == `INSN_reg_dHL) begin - address <= {registers[`REG_H], registers[`REG_L]}; - wdata <= rdata; - rd <= 0; - wr <= 1; - end else begin - `EXEC_NEWCYCLE; - end - end - 2: begin - `EXEC_NEWCYCLE; + `EXEC_INC_PC + if (opcode[5:3] == `INSN_reg_dHL) + `EXEC_WRITE(`_HL, rdata) + else + `EXEC_NEWCYCLE end + 2: `EXEC_NEWCYCLE endcase end `endif @@ -29,13 +22,13 @@ case (cycle) 0: begin end 1: case (opcode[5:3]) - `INSN_reg_A: begin registers[`REG_A] <= rdata; end - `INSN_reg_B: begin registers[`REG_B] <= rdata; end - `INSN_reg_C: begin registers[`REG_C] <= rdata; end - `INSN_reg_D: begin registers[`REG_D] <= rdata; end - `INSN_reg_E: begin registers[`REG_E] <= rdata; end - `INSN_reg_H: begin registers[`REG_H] <= rdata; end - `INSN_reg_L: begin registers[`REG_L] <= rdata; end + `INSN_reg_A: begin `_A <= rdata; end + `INSN_reg_B: begin `_B <= rdata; end + `INSN_reg_C: begin `_C <= rdata; end + `INSN_reg_D: begin `_D <= rdata; end + `INSN_reg_E: begin `_E <= rdata; end + `INSN_reg_H: begin `_H <= rdata; end + `INSN_reg_L: begin `_L <= rdata; end `INSN_reg_dHL: begin /* Go off to cycle 2 */ end endcase 2: begin end diff --git a/insn_ld_reg_reg.v b/insn_ld_reg_reg.v index 4b5081e..7bbea95 100644 --- a/insn_ld_reg_reg.v +++ b/insn_ld_reg_reg.v @@ -1,15 +1,15 @@ `ifdef EXECUTE `INSN_LD_reg_reg: begin - `EXEC_INC_PC; - `EXEC_NEWCYCLE; + `EXEC_INC_PC + `EXEC_NEWCYCLE case (opcode[2:0]) - `INSN_reg_A: tmp <= registers[`REG_A]; - `INSN_reg_B: tmp <= registers[`REG_B]; - `INSN_reg_C: tmp <= registers[`REG_C]; - `INSN_reg_D: tmp <= registers[`REG_D]; - `INSN_reg_E: tmp <= registers[`REG_E]; - `INSN_reg_H: tmp <= registers[`REG_H]; - `INSN_reg_L: tmp <= registers[`REG_L]; + `INSN_reg_A: tmp <= `_A; + `INSN_reg_B: tmp <= `_B; + `INSN_reg_C: tmp <= `_C; + `INSN_reg_D: tmp <= `_D; + `INSN_reg_E: tmp <= `_E; + `INSN_reg_H: tmp <= `_H; + `INSN_reg_L: tmp <= `_L; endcase end `endif @@ -17,13 +17,13 @@ `ifdef WRITEBACK `INSN_LD_reg_reg: begin case (opcode[5:3]) - `INSN_reg_A: registers[`REG_A] <= tmp; - `INSN_reg_B: registers[`REG_B] <= tmp; - `INSN_reg_C: registers[`REG_C] <= tmp; - `INSN_reg_D: registers[`REG_D] <= tmp; - `INSN_reg_E: registers[`REG_E] <= tmp; - `INSN_reg_H: registers[`REG_H] <= tmp; - `INSN_reg_L: registers[`REG_L] <= tmp; + `INSN_reg_A: `_A <= tmp; + `INSN_reg_B: `_B <= tmp; + `INSN_reg_C: `_C <= tmp; + `INSN_reg_D: `_D <= tmp; + `INSN_reg_E: `_E <= tmp; + `INSN_reg_H: `_H <= tmp; + `INSN_reg_L: `_L <= tmp; endcase end `endif diff --git a/insn_ld_sp_hl.v b/insn_ld_sp_hl.v index ba10d5a..3d4fc18 100644 --- a/insn_ld_sp_hl.v +++ b/insn_ld_sp_hl.v @@ -1,13 +1,11 @@ `ifdef EXECUTE `INSN_LD_SP_HL: begin case (cycle) - 0: begin - tmp <= registers[`REG_H]; - end + 0: tmp <= `_H; 1: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; - tmp <= registers[`REG_L]; + `EXEC_NEWCYCLE + `EXEC_INC_PC + tmp <= `_L; end endcase end @@ -16,8 +14,8 @@ `ifdef WRITEBACK `INSN_LD_SP_HL: begin case (cycle) - 0: registers[`REG_SPH] <= tmp; - 1: registers[`REG_SPL] <= tmp; + 0: `_SPH <= tmp; + 1: `_SPL <= tmp; endcase end `endif diff --git a/insn_ldh_ac.v b/insn_ldh_ac.v index 146f10b..a2ff5cc 100644 --- a/insn_ldh_ac.v +++ b/insn_ldh_ac.v @@ -1,18 +1,13 @@ `ifdef EXECUTE `INSN_LDH_AC: begin case (cycle) - 0: begin - address <= {8'hFF,registers[`REG_C]}; - if (opcode[4]) begin // LD A,(C) - rd <= 1; - end else begin - wr <= 1; - wdata <= registers[`REG_A]; - end - end + 0: if (opcode[4]) // LD A,(C) + `EXEC_READ(({8'hFF,`_C})) + else + `EXEC_WRITE(({8'hFF,`_C}), `_A) 1: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC end endcase end @@ -22,8 +17,7 @@ `INSN_LDH_AC: begin case (cycle) 0: begin /* Type F */ end - 1: if (opcode[4]) - registers[`REG_A] <= rdata; + 1: if (opcode[4]) `_A <= rdata; endcase end `endif diff --git a/insn_ldx_ahl.v b/insn_ldx_ahl.v index a16d6ba..a2d2420 100644 --- a/insn_ldx_ahl.v +++ b/insn_ldx_ahl.v @@ -1,18 +1,13 @@ `ifdef EXECUTE `INSN_LDx_AHL: begin case (cycle) - 0: begin - address <= {registers[`REG_H],registers[`REG_L]}; - if (opcode[3]) begin // LDx A, (HL) - rd <= 1; - end else begin - wr <= 1; - wdata <= registers[`REG_A]; - end - end + 0: if (opcode[3]) // LDx A, (HL) + `EXEC_READ(`_HL) + else + `EXEC_WRITE(`_HL, `_A) 1: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC end endcase end @@ -24,11 +19,10 @@ 0: begin /* Type F */ end 1: begin if (opcode[3]) - registers[`REG_A] <= rdata; - {registers[`REG_H],registers[`REG_L]} <= - opcode[4] ? // if set, LDD, else LDI - ({registers[`REG_H],registers[`REG_L]} - 1) : - ({registers[`REG_H],registers[`REG_L]} + 1); + `_A <= rdata; + `_HL <= opcode[4] ? // if set, LDD, else LDI + (`_HL - 1) : + (`_HL + 1); end endcase end diff --git a/insn_nop.v b/insn_nop.v index 2772a11..9270c88 100644 --- a/insn_nop.v +++ b/insn_nop.v @@ -1,7 +1,7 @@ `ifdef EXECUTE `INSN_NOP: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC end `endif diff --git a/insn_pop_reg.v b/insn_pop_reg.v index 9d4acbd..5a7da08 100644 --- a/insn_pop_reg.v +++ b/insn_pop_reg.v @@ -1,17 +1,11 @@ `ifdef EXECUTE `INSN_POP_reg: begin /* POP is 12 cycles! */ case (cycle) - 0: begin - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}; - end - 1: begin - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1; - end + 0: `EXEC_READ(`_SP) + 1: `EXEC_READ(`_SP + 1) 2: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC end endcase end @@ -23,21 +17,20 @@ 0: begin end 1: begin case (opcode[5:4]) - `INSN_stack_AF: registers[`REG_F] <= rdata; - `INSN_stack_BC: registers[`REG_C] <= rdata; - `INSN_stack_DE: registers[`REG_E] <= rdata; - `INSN_stack_HL: registers[`REG_L] <= rdata; + `INSN_stack_AF: `_F <= rdata; + `INSN_stack_BC: `_C <= rdata; + `INSN_stack_DE: `_E <= rdata; + `INSN_stack_HL: `_L <= rdata; endcase end 2: begin case (opcode[5:4]) - `INSN_stack_AF: registers[`REG_A] <= rdata; - `INSN_stack_BC: registers[`REG_B] <= rdata; - `INSN_stack_DE: registers[`REG_D] <= rdata; - `INSN_stack_HL: registers[`REG_H] <= rdata; + `INSN_stack_AF: `_A <= rdata; + `INSN_stack_BC: `_B <= rdata; + `INSN_stack_DE: `_D <= rdata; + `INSN_stack_HL: `_H <= rdata; endcase - {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]} + 2; + `_SP <= `_SP + 2; end endcase end diff --git a/insn_push_reg.v b/insn_push_reg.v index 7a32301..afec70a 100644 --- a/insn_push_reg.v +++ b/insn_push_reg.v @@ -1,30 +1,22 @@ `ifdef EXECUTE `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */ case (cycle) - 0: begin - wr <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; - case (opcode[5:4]) - `INSN_stack_AF: wdata <= registers[`REG_A]; - `INSN_stack_BC: wdata <= registers[`REG_B]; - `INSN_stack_DE: wdata <= registers[`REG_D]; - `INSN_stack_HL: wdata <= registers[`REG_H]; - endcase - end - 1: begin - wr <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}-2; - case (opcode[5:4]) - `INSN_stack_AF: wdata <= registers[`REG_F]; - `INSN_stack_BC: wdata <= registers[`REG_C]; - `INSN_stack_DE: wdata <= registers[`REG_E]; - `INSN_stack_HL: wdata <= registers[`REG_L]; - endcase - end + 0: case (opcode[5:4]) + `INSN_stack_AF: `EXEC_WRITE(`_SP - 1, `_A) + `INSN_stack_BC: `EXEC_WRITE(`_SP - 1, `_B) + `INSN_stack_DE: `EXEC_WRITE(`_SP - 1, `_D) + `INSN_stack_HL: `EXEC_WRITE(`_SP - 1, `_H) + endcase + 1: case (opcode[5:4]) + `INSN_stack_AF: `EXEC_WRITE(`_SP - 1, `_F) + `INSN_stack_BC: `EXEC_WRITE(`_SP - 1, `_C) + `INSN_stack_DE: `EXEC_WRITE(`_SP - 1, `_E) + `INSN_stack_HL: `EXEC_WRITE(`_SP - 1, `_L) + endcase 2: begin /* Twiddle thumbs. */ end 3: begin - `EXEC_NEWCYCLE; - `EXEC_INC_PC; + `EXEC_NEWCYCLE + `EXEC_INC_PC end endcase end @@ -36,8 +28,7 @@ 0: begin /* type F */ end 1: begin /* type F */ end 2: begin /* type F */ end - 3: {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]} - 2; + 3: `_SP <= `_SP - 2; endcase end `endif diff --git a/insn_ret-retcc.v b/insn_ret-retcc.v index ef89003..bad4c04 100644 --- a/insn_ret-retcc.v +++ b/insn_ret-retcc.v @@ -1,30 +1,20 @@ `ifdef EXECUTE `INSN_RET,`INSN_RETCC: begin case (cycle) - 0: begin - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}; - end + 0: `EXEC_READ(`_SP) 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret! - `EXEC_INC_PC; // cycle 1 is skipped if we are not retcc + `EXEC_INC_PC // cycle 1 is skipped if we are not retcc case (opcode[4:3]) - `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end - `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end - `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NZ: if (registers[`REG_F][7]) `EXEC_NEWCYCLE + `INSN_cc_Z: if (~registers[`REG_F][7]) `EXEC_NEWCYCLE + `INSN_cc_NC: if (registers[`REG_F][4]) `EXEC_NEWCYCLE + `INSN_cc_C: if (~registers[`REG_F][4]) `EXEC_NEWCYCLE endcase - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}; - end - 2: begin - rd <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1; + `EXEC_READ(`_SP) // retry the read end + 2: `EXEC_READ(`_SP + 1) 3: begin /* twiddle thumbs */ end - 4: begin - `EXEC_NEWCYCLE; - // do NOT increment PC! - end + 4: `EXEC_NEWCYCLE endcase end `endif @@ -35,11 +25,10 @@ 0: if (opcode[0]) // i.e., not RETCC cycle <= 1; // Skip cycle 1; it gets incremented on the next round. 1: begin /* Nothing need happen here. */ end - 2: registers[`REG_PCL] <= rdata; - 3: registers[`REG_PCH] <= rdata; + 2: `_PCL <= rdata; + 3: `_PCH <= rdata; 4: begin - {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]} + 2; + `_SP <= `_SP + 2; if (opcode[4] && opcode[0]) /* RETI */ ie <= 1; end diff --git a/insn_rst.v b/insn_rst.v index 8752034..4b65032 100644 --- a/insn_rst.v +++ b/insn_rst.v @@ -1,23 +1,12 @@ `ifdef EXECUTE `INSN_RST: begin case (cycle) - 0: begin - `EXEC_INC_PC; // This goes FIRST in RST - end - 1: begin - wr <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; - wdata <= registers[`REG_PCH]; - end - 2: begin - wr <= 1; - address <= {registers[`REG_SPH],registers[`REG_SPL]}-2; - wdata <= registers[`REG_PCL]; - end + 0: `EXEC_INC_PC // This goes FIRST in RST + 1: `EXEC_WRITE(`_SP - 1, `_PCH) + 2: `EXEC_WRITE(`_SP - 2, `_PCL) 3: begin - `EXEC_NEWCYCLE; - {registers[`REG_PCH],registers[`REG_PCL]} <= - {10'b0,opcode[5:3],3'b0}; + `EXEC_NEWCYCLE + `_PC <= {10'b0,opcode[5:3],3'b0}; end endcase end @@ -29,8 +18,7 @@ 0: begin /* type F */ end 1: begin /* type F */ end 2: begin /* type F */ end - 3: {registers[`REG_SPH],registers[`REG_SPL]} <= - {registers[`REG_SPH],registers[`REG_SPL]}-2; + 3: `_SP <= `_SP - 2; endcase end `endif diff --git a/insn_vop_intr.v b/insn_vop_intr.v index 06218f4..5cb40e1 100644 --- a/insn_vop_intr.v +++ b/insn_vop_intr.v @@ -1,9 +1,9 @@ `ifdef EXECUTE `INSN_VOP_INTR: begin case (cycle) - 0: `EXEC_WRITE(`_SP - 1, `_PCH); - 1: `EXEC_WRITE(`_SP - 2, `_PCL); - 2: `EXEC_NEWCYCLE; + 0: `EXEC_WRITE(`_SP - 1, `_PCH) + 1: `EXEC_WRITE(`_SP - 2, `_PCL) + 2: `EXEC_NEWCYCLE endcase end `endif -- 2.39.2