From 4d90f272baf43caf90927ca7e893518d526649e5 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@nyus.joshuawise.com>
Date: Fri, 18 Apr 2008 06:29:43 -0400
Subject: [PATCH] Cut 1 at output

---
 LCDC.v   | 57 ++++++++++++++++++++++++++++----------------------------
 diag.asm | 52 ++++++++++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 77 insertions(+), 32 deletions(-)

diff --git a/LCDC.v b/LCDC.v
index 8f237eb..a8bec01 100644
--- a/LCDC.v
+++ b/LCDC.v
@@ -74,11 +74,14 @@ module LCDC(
 				 2'b00)
 				: 2'b01;
 	
+	wire [7:0] vxpos = rSCX + posx - 3;
+	wire [7:0] vypos = rSCY + posy;
+	
 	assign lcdvs = (posy == 153) && (posx == 455);
 	assign lcdhs = (posx == 455);
 	assign lcdr = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
 	assign lcdg = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
-	assign lcdb = display ? {posy < rSCY ? 2'b11 : 2'b00} : 2'b00;
+	assign lcdb = display ? {(vypos < 8) ? 2'b11 : 2'b00} : 2'b00;
 	
 	reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
 	assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
@@ -123,47 +126,42 @@ module LCDC(
 	 * Tile data from 8000-8FFF or 8800-97FF
 	 * Background tile maps 9800-9BFF or 9C00-9FFF
 	 */
-	reg [7:0] tiledata [6143:0];
+	reg [7:0] tiledatahigh [3071:0];
+	reg [7:0] tiledatalow [3071:0];
 	reg [7:0] bgmap1 [1023:0];
 	reg [7:0] bgmap2 [1023:0];
 	
 	// Upper five bits are Y coord, lower five bits are X coord
-	wire [7:0] vxpos = rSCX + posx - 3;
-	wire [7:0] vypos = rSCY + posy;
-	
-	// The new tile number is loaded when vxpos[2:0] is 3'b101
-	// The new tile data low is loaded when vxpos[2:0] is 3'b110
-	// The new tile data high is loaded when vxpos[2:0] is 3'b111
+	// The new tile number is loaded when vxpos[2:0] is 3'b110
+	// The new tile data is loaded when vxpos[2:0] is 3'b111
 	// The new tile data is latched and ready when vxpos[2:0] is 3'b000!
 	wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]};
 	reg [7:0] tileno;
 	wire [10:0] tileaddr = {tileno, vypos[2:1]};
-	reg [7:0] tilelowtmp, tilehigh, tilelow;
+	reg [7:0] tilehigh, tilelow;
 	assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]};
 	
 	wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
 	wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
+
+	wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
+	wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
 	
 	always @(negedge clk)
-		if (vraminuse) begin
-			if ((posx == 0) || ((posx > 2) && (vxpos[2:0] == 3'b101)))
-				tileno <= bgmap1[bgmapaddr];
-			else if ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110)))
-				tilelowtmp <= tiledata[{tileaddr, 1'b0}];
-			else if ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111))) begin
-				tilehigh <= tiledata[{tileaddr, 1'b1}];
-				tilelow <= tilelowtmp;
-			end
-		end else begin
-			if (decode_tiledata) begin
-				tilelowtmp <= tiledata[addr[12:0]];
-				if (wr)
-					tiledata[addr[12:0]] <= data;
-			end else if (decode_bgmap1) begin
-				tileno <= bgmap1[addr[12:0]];
-				if (wr)
-					bgmap1[addr[12:0]] <= data;
-			end
+		if ((vraminuse && ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110)))) || decode_bgmap1) begin
+			tileno <= bgmap1[bgmapaddr_in];
+			if (wr && decode_bgmap1)
+				bgmap1[bgmapaddr_in] <= data;
+		end
+	
+	always @(negedge clk)
+		if ((vraminuse && ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111)))) || decode_tiledata) begin
+			tilehigh <= tiledatahigh[tileaddr_in];
+			tilelow <= tiledatalow[tileaddr_in];
+			if (wr && addr[0] && decode_tiledata)
+				tiledatahigh[tileaddr_in] <= data;
+			if (wr && ~addr[0] && decode_tiledata)
+				tiledatalow[tileaddr_in] <= data;
 		end
   
 	/***** Bus interface *****/
@@ -179,7 +177,8 @@ module LCDC(
 			(addr == `ADDR_OBP1) ? rOBP1 :
 			(addr == `ADDR_WY) ? rWY :
 			(addr == `ADDR_WX) ? rWX :
-			(decode_tiledata) ? tilelowtmp :
+			(decode_tiledata && addr[0]) ? tilehigh :
+			(decode_tiledata && ~addr[0]) ? tilelow :
 			(decode_bgmap1) ? tileno :
 			8'bzzzzzzzz :
 		8'bzzzzzzzz;
diff --git a/diag.asm b/diag.asm
index 7f06de0..bc164a0 100644
--- a/diag.asm
+++ b/diag.asm
@@ -51,16 +51,57 @@ signon:
 	db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
 
 putscreen:
-	ld a, $FF		; Copy two tiles.
-	ld hl, $8000
+	; Wait for vblank
+;.stat:	ld a, [$FF41]	; STAT
+;	and $03		; mode
+;	cp $01		; VBLANK
+;'	jp nz, .stat
+
+	ld hl, $8000	; Copy two tiles.
+	ld a, $AA
+	ld [hli], a
+	ld [hli], a
+	ld a, $55
+	ld [hli], a
+	ld [hli], a
+	ld a, $AA
+	ld [hli], a
+	ld [hli], a
+	ld a, $55
+	ld [hli], a
+	ld [hli], a
+	ld a, $AA
+	ld [hli], a
+	ld [hli], a
+	ld a, $55
+	ld [hli], a
+	ld [hli], a
+	ld a, $AA
+	ld [hli], a
+	ld [hli], a
+	ld a, $55
 	ld [hli], a
 	ld [hli], a
 	xor a
 	ld [hli], a
 	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
+	ld [hli], a
 	
 	ld hl, $9800
-.loop:	ld a, $FF
+.loop:	ld a, $01
 	ld [hli], a
 	xor a
 	ld [hli], a
@@ -82,6 +123,11 @@ vbl:
 	ld a, [c]
 	inc a
 	ld [c], a
+	
+	ld c, $43	; SCX
+	ld a, [c]
+	inc a
+	ld [c], a
 
 	POP HL
 	POP DE
-- 
2.39.2