From: Joshua Wise Date: Wed, 2 Apr 2008 03:48:24 +0000 (-0400) Subject: Add files, and add a freezeswitch to debug this issue with push no type check. X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/ff7fd7f2e78ed70833e58cecc316d5c8d6603349?ds=inline Add files, and add a freezeswitch to debug this issue with push no type check. --- diff --git a/7seg.v b/7seg.v new file mode 100644 index 0000000..ed4519a --- /dev/null +++ b/7seg.v @@ -0,0 +1,58 @@ +module AddrMon( + input [15:0] addr, + input clk, + output reg [3:0] digit, + output reg [7:0] out, + input freeze + ); + + reg [12:0] clkdv; + reg [1:0] dcount; + + reg [15:0] latch = 0; + + wire [3:0] curval = + (dcount == 2'b00) ? latch[3:0] : + (dcount == 2'b01) ? latch[7:4] : + (dcount == 2'b10) ? latch[11:8] : + latch[15:12]; + + always @ (negedge clk) + begin + clkdv <= clkdv + 1; + if (~freeze) + latch <= addr; + end + + always @ (posedge clkdv[12]) + begin + dcount <= dcount + 1; + + case(dcount) + 2'b00: digit <= 4'b1110; + 2'b01: digit <= 4'b1101; + 2'b10: digit <= 4'b1011; + 2'b11: digit <= 4'b0111; + endcase + + case(curval) + /* ABCDEFGP */ + 4'h0: out <= ~8'b11111100; + 4'h1: out <= ~8'b01100000; + 4'h2: out <= ~8'b11011010; + 4'h3: out <= ~8'b11110010; + 4'h4: out <= ~8'b01100110; + 4'h5: out <= ~8'b10110110; + 4'h6: out <= ~8'b10111110; + 4'h7: out <= ~8'b11100000; + 4'h8: out <= ~8'b11111110; + 4'h9: out <= ~8'b11110110; + 4'hA: out <= ~8'b11101110; + 4'hB: out <= ~8'b00111110; + 4'hC: out <= ~8'b10011100; + 4'hD: out <= ~8'b01111010; + 4'hE: out <= ~8'b10011110; + 4'hF: out <= ~8'b10001110; + endcase + end +endmodule diff --git a/CoreTop.ucf b/CoreTop.ucf new file mode 100644 index 0000000..6cbca7e --- /dev/null +++ b/CoreTop.ucf @@ -0,0 +1,39 @@ +NET "xtal" LOC="B8"; +NET "serio" LOC = "p9"; + +NET "leds<0>" LOC = "j14" ; +NET "leds<1>" LOC = "j15" ; +NET "leds<2>" LOC = "k15" ; +NET "leds<3>" LOC = "k14" ; +NET "leds<4>" LOC = "e17" ; +NET "leds<5>" LOC = "p15" ; +NET "leds<6>" LOC = "f4" ; +NET "leds<7>" LOC = "r4" ; + +NET "switches<7>" LOC="r17"; +NET "switches<6>" LOC="n17"; +NET "switches<5>" LOC="l13"; +NET "switches<4>" LOC="l14"; +NET "switches<3>" LOC="k17"; +NET "switches<2>" LOC="k18"; +NET "switches<1>" LOC="h18"; +NET "switches<0>" LOC="g18"; + +NET "seven<7>" LOC="L18"; +NET "seven<6>" LOC="F18"; +NET "seven<5>" LOC="D17"; +NET "seven<4>" LOC="D16"; +NET "seven<3>" LOC="G14"; +NET "seven<2>" LOC="J17"; +NET "seven<1>" LOC="H14"; +NET "seven<0>" LOC="C17"; + +NET "digits<0>" LOC="F17"; +NET "digits<1>" LOC="H17"; +NET "digits<2>" LOC="C18"; +NET "digits<3>" LOC="F15"; + +NET "buttons<0>" LOC="H13"; +NET "buttons<1>" LOC="E18"; +NET "buttons<2>" LOC="D18"; +NET "buttons<3>" LOC="B18"; diff --git a/FPGABoy.ise b/FPGABoy.ise index 35dc92f..d4a916a 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/System.v b/System.v index 8fc4c9c..033e4b1 100644 --- a/System.v +++ b/System.v @@ -61,6 +61,7 @@ endmodule module CoreTop( input xtal, input [7:0] switches, + input [3:0] buttons, output wire [7:0] leds, output serio, output wire [3:0] digits, @@ -93,7 +94,8 @@ module CoreTop( .addr(addr), .clk(clk), .digit(digits), - .out(seven) + .out(seven), + .freeze(buttons[0]) ); Switches sw( diff --git a/rom.hex b/rom.hex index 0e894fb..6d9f1d9 100644 --- a/rom.hex +++ b/rom.hex @@ -2,16 +2,14 @@ ff df 21 -18 +16 00 0e 50 06 00 -f2 -b8 -c2 -0a +cd +23 00 2a b8 @@ -35,10 +33,12 @@ c3 21 20 00 +f2 +b8 +c2 +23 00 -00 -00 -00 +c9 00 00 00