From: Joshua Wise Date: Sun, 13 Apr 2008 07:29:25 +0000 (-0400) Subject: Add DI/EI delay test. Add LD M, A. X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/f9000d73c8971e2e6323122efb06bcfd846b5d62?ds=inline;hp=f2b745a710572fd5cb2b1cf97d1d05a9b74d4fe1 Add DI/EI delay test. Add LD M, A. --- diff --git a/FPGABoy.ise b/FPGABoy.ise index c324dd0..ea94f12 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/GBZ80Core.v b/GBZ80Core.v index 33e7be6..3bbaee8 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -71,6 +71,7 @@ `define INSN_EI 8'b11111011 `define INSN_INCDEC_HL 8'b0011010x `define INSN_INCDEC_reg8 8'b00xxx10x +`define INSN_LDM_A 8'b111xx000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 `define INSN_cc_NZ 2'b00 `define INSN_cc_Z 2'b01 diff --git a/allinsns.v b/allinsns.v index 0b2e51c..085389b 100644 --- a/allinsns.v +++ b/allinsns.v @@ -22,4 +22,5 @@ `include "insn_vop_intr.v" `include "insn_di-ei.v" `include "insn_incdec_hl.v" -`include "insn_incdec_reg8.v" \ No newline at end of file +`include "insn_incdec_reg8.v" +`include "insn_ldm_a.v" \ No newline at end of file diff --git a/diag.asm b/diag.asm index 786052e..55127f8 100644 --- a/diag.asm +++ b/diag.asm @@ -52,11 +52,10 @@ irqhand: ld a, $41 ; print A call putc .noprint: + inc [hl] ld a, [hl] - add 1 ld c, $51 ld [c], a - ld [hl], a POP HL POP DE @@ -235,11 +234,32 @@ insntest: cpl cp $AA jr nz,.fail + + ; Test DI/EI delay + di + ld hl, .difail + ld c, $0F ; First, wait until an interrupt happens... +.wait: ld a, [c] + cp 0 + jr z, .wait + ei ; Now make sure that an IRQ didn't happen on EI/DI + di + ld a, [c] + cp 0 + jr z, .fail + ei ; Make sure that an IRQ does happen on EI/NOP/DI + nop + di + ld a, [c] + cp 0 + jr nz, .fail + ei ld hl, .ok call puts ret .fail: + ei call puts ld hl, .testfailed call puts @@ -262,6 +282,8 @@ insntest: db "CPL",0 .inc16fail: db "INC16",0 +.difail: + db "DI/EI delay",0 .testfailed: db " test failed.",$0D,$0A,0 .ok: diff --git a/insn_ldm_a.v b/insn_ldm_a.v new file mode 100644 index 0000000..485b6a4 --- /dev/null +++ b/insn_ldm_a.v @@ -0,0 +1,43 @@ +// If opcode[4], then ld A, x, else ld x, A +// If opcode[1], then ld 16m8, else ld 8m8 + +`ifdef EXECUTE + `INSN_LDM_A: begin + case (cycle) + 0: begin + `EXEC_INC_PC + `EXEC_READ(`_PC + 16'h0001) + end + 1: begin + `EXEC_INC_PC // we only hit here if 16m8 + `EXEC_READ(`_PC + 16'h0001) + end + 2: if (opcode[4]) // LD A,x + `EXEC_READ(({tmp, tmp2})) + else + `EXEC_WRITE(({tmp, tmp2}), `_A) + 3: begin + `EXEC_NEWCYCLE + `EXEC_INC_PC + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_LDM_A: begin + case (cycle) + 0: if (!opcode[1]) begin + tmp <= 8'hFF; + cycle <= 1; /* Skip cycle 1 */ + end + 1: tmp2 <= rdata; + 2: if (opcode[1]) + tmp2 <= rdata; + else + tmp <= rdata; + 3: if (opcode[4]) `_A <= rdata; + endcase + end +`endif + diff --git a/opcodes b/opcodes new file mode 100644 index 0000000..6a54b02 --- /dev/null +++ b/opcodes @@ -0,0 +1,127 @@ +YET UNIMPLEMENTED: + +imm3 = 3-bit immediate value in 8 bits +imm8 = 8-bit immediate value +imm16 = 16-bit immediate value +16m8 = 8-bit value at the 16-bit address +8m8 = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr) + +bits insn notes +0000 0010 LD (BC), A +0000 1000 LD 16m16,SP loads SP +0000 1001 ADD HL, BC +0000 1010 LD A, (BC) +0001 0000 STOP +0001 0010 LD (DE), A +0001 1001 ADD HL, DE +0001 1010 LD A, (DE) +0010 1001 ADD HL, HL +0011 1001 ADD HL, SP +0111 0110 HALT Danger! Helvetica! +1100 1011 - - - see two-byte opcodes below +1110 1000 ADD SP, imm8 +1111 1000 LDHL SP, imm8 load SP+n (signed n) into HL + +***************************** + +fucking two-byte opcodes + +bits insn notes +1100 1011 0000 0000 RLC B +1100 1011 0000 0001 RLC C +1100 1011 0000 0010 RLC D +1100 1011 0000 0011 RLC E +1100 1011 0000 0100 RLC H +1100 1011 0000 0101 RLC L +1100 1011 0000 0110 RLC (HL) +1100 1011 0000 0111 RLC A + +1100 1011 0000 1000 RRC B +1100 1011 0000 1001 RRC C +1100 1011 0000 1010 RRC D +1100 1011 0000 1011 RRC E +1100 1011 0000 1100 RRC H +1100 1011 0000 1101 RRC L +1100 1011 0000 1110 RRC (HL) +1100 1011 0000 1111 RRC A + +1100 1011 0001 0000 RL B +1100 1011 0001 0001 RL C +1100 1011 0001 0010 RL D +1100 1011 0001 0011 RL E +1100 1011 0001 0100 RL H +1100 1011 0001 0101 RL L +1100 1011 0001 0110 RL (HL) +1100 1011 0001 0111 RL A + +1100 1011 0001 1000 RR B +1100 1011 0001 1001 RR C +1100 1011 0001 1010 RR D +1100 1011 0001 1011 RR E +1100 1011 0001 1100 RR H +1100 1011 0001 1101 RR L +1100 1011 0001 1110 RR (HL) +1100 1011 0001 1111 RR A + +1100 1011 0010 0000 SLA B +1100 1011 0010 0001 SLA C +1100 1011 0010 0010 SLA D +1100 1011 0010 0011 SLA E +1100 1011 0010 0100 SLA H +1100 1011 0010 0101 SLA L +1100 1011 0010 0110 SLA (HL) +1100 1011 0010 0111 SLA A + +1100 1011 0010 1000 SRA B +1100 1011 0010 1001 SRA C +1100 1011 0010 1010 SRA D +1100 1011 0010 1011 SRA E +1100 1011 0010 1100 SRA H +1100 1011 0010 1101 SRA L +1100 1011 0010 1110 SRA (HL) +1100 1011 0010 1111 SRA A + +1100 1011 0011 1000 SRL B +1100 1011 0011 1001 SRL C +1100 1011 0011 1010 SRL D +1100 1011 0011 1011 SRL E +1100 1011 0011 1100 SRL H +1100 1011 0011 1101 SRL L +1100 1011 0011 1110 SRL (HL) +1100 1011 0011 1111 SRL A + +1100 1011 0011 0000 SWAP B swaps upper and lower nibbles of a byte +1100 1011 0011 0001 SWAP C +1100 1011 0011 0010 SWAP D +1100 1011 0011 0011 SWAP E +1100 1011 0011 0100 SWAP H +1100 1011 0011 0101 SWAP L +1100 1011 0011 0110 SWAP (HL) +1100 1011 0011 0111 SWAP A + +1100 1011 0100 0000 BIT imm3, B test bit specified by imm3 +1100 1011 0100 0001 BIT imm3, C +1100 1011 0100 0010 BIT imm3, D +1100 1011 0100 0011 BIT imm3, E +1100 1011 0100 0100 BIT imm3, H +1100 1011 0100 0101 BIT imm3, L +1100 1011 0100 0110 BIT imm3, (HL) +1100 1011 0100 0111 BIT imm3, A + +1100 1011 1000 0000 RES imm3, B reset bit specified by imm3 +1100 1011 1000 0001 RES imm3, C +1100 1011 1000 0010 RES imm3, D +1100 1011 1000 0011 RES imm3, E +1100 1011 1000 0100 RES imm3, H +1100 1011 1000 0101 RES imm3, L +1100 1011 1000 0110 RES imm3, (HL) +1100 1011 1000 0111 RES imm3, A + +1100 1011 1100 0000 SET imm3, B set bit specified by imm3 +1100 1011 1100 0001 SET imm3, C +1100 1011 1100 0010 SET imm3, D +1100 1011 1100 0011 SET imm3, E +1100 1011 1100 0100 SET imm3, H +1100 1011 1100 0101 SET imm3, L +1100 1011 1100 0110 SET imm3, (HL) +1100 1011 1100 0111 SET imm3, A diff --git a/rom.asm b/rom.asm index cf8fd60..1a2221f 100644 --- a/rom.asm +++ b/rom.asm @@ -43,11 +43,10 @@ irqhand: call putc ld hl, $DF81 + inc [hl] ld a, [hl] - add 1 ld c, $51 ld [c], a - ld [hl], a POP HL