From: Joshua Wise Date: Sun, 11 May 2008 12:18:03 +0000 (-0400) Subject: Merge branch 'master' of andrew:/afs/andrew/usr/czl/public/FPGABoy X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/f327eee1f228769c4753a3f2279063c99f6f1ab0?hp=8e36c4ed64993143adcbf103a7d4e4bc1ec627a1 Merge branch 'master' of andrew:/afs/andrew/usr/czl/public/FPGABoy --- diff --git a/core/insn_alu_a.v b/core/insn_alu_a.v index a5e1c1c..80d317d 100644 --- a/core/insn_alu_a.v +++ b/core/insn_alu_a.v @@ -35,6 +35,78 @@ `_A <= {`_F[4],`_A[7:1]}; `_F <= {`_F[7:5],`_A[0],`_F[3:0]}; end + `INSN_alu_DAA: begin + if (`_F[6]) begin + if (`_F[4]) begin + if(`_A[3:0] >= 4'h6 && `_A[7:4] >= 4'h6 && `F[5]) begin + `_A <= `_A + 8'h9A; + `_F <= {((`_A + 8'h9A) == 8'b0), `_F[6:0]}; + end + else begin + `_A <= `_A + 8'hA0; + `_F <= {((`_A + 8'hA0) == 8'b0), `_F[6:0]}; + end + end + else begin + if(`_A[3:0] <= 4'h9 && `_A[7:4] <= 4'h9 && !`_F[5]) begin + `_F <= {(`_A == 8'b0), `_F[6:0]}; + end + else begin + `_A <= `_A + 8'hFA; + `_F <= {((`_A + 8'hFA) == 8'b0), `_F[6:0]}; + end + end + end + else begin + if (`_F[4]) begin + if(`_F[5]) begin + `_A <= `_A + 8'h66; + `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]}; + end + else if (`_A[3:0] > 4'b9) begin + `_A <= `_A + 8'h66; + `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]}; + end + else begin + `_A <= `_A + 8'h60; + `_F <= {((`_A + 8'h60) == 8'b0), `_F[6:0]}; + end + end + else begin + if(`_F[5]) begin + if(`_A[7:4] > 4'h9) begin + `_A <= `_A + 8'h66; + `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]}; + end + else begin + `_A <= `_A + 8'h06; + `_F <= {((`_A + 8'h06) == 8'b0), `_F[6:0]}; + end + end + else begin + if(`_A[3:0] > 4'h9) begin + if (`_A[7:4] > 4'h8) begin + `_A <= `_A + 8'h66; + `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]}; + end + else begin + `_A <= `_A + 8'h06; + `_F <= {((`_A + 8'h06) == 8'b0), `_F[6:0]}; + end + end + else begin + if (`_A[7:4] > 4'h9) begin + `_A <= `_A + 8'h66; + `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]}; + end + else begin + `_F <= {(`_A == 8'b0), `_F[6:0]}; + end + end + end + end + end + end `INSN_alu_CPL: begin `_A <= ~`_A; `_F <= {`_F[7],1'b1,1'b1,`_F[4:0]};