From: Joshua Wise Date: Fri, 4 Apr 2008 06:10:58 +0000 (-0400) Subject: Yay. Fix retcc. Comparing against an x value - great idea, or greatest idea? X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/f26748f71f3f39de15a1c07f95c15f8c4481f452?hp=611e4a90d4f4c5b5e2cadde0da57639bfbaca6a8 Yay. Fix retcc. Comparing against an x value - great idea, or greatest idea? --- diff --git a/FPGABoy.ise b/FPGABoy.ise index b09f383..1d807e9 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/GBZ80Core.v b/GBZ80Core.v index cd7f4d1..3cd46e3 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -401,7 +401,7 @@ module GBZ80Core( end endcase end - `INSN_RET: begin + `INSN_RET,`INSN_RETCC: begin case (cycle) 0: begin rd <= 1; @@ -409,8 +409,6 @@ module GBZ80Core( end 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret! `EXEC_INC_PC; - if (opcode != `INSN_RETCC) - $stop; case (opcode[4:3]) // cycle 1 is skipped if we are not retcc `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end @@ -794,7 +792,7 @@ module GBZ80Core( end `INSN_RET,`INSN_RETCC: begin case (cycle) - 0: if (opcode != `INSN_RETCC) + 0: if (opcode[0]) // i.e., not RETCC cycle <= 1; // Skip cycle 1; it gets incremented on the next round. 1: begin /* Nothing need happen here. */ end 2: registers[`REG_PCL] <= rdata; diff --git a/rom.asm b/rom.asm index aa070ff..d650855 100644 --- a/rom.asm +++ b/rom.asm @@ -212,7 +212,7 @@ insntest: .cplfail: db "CPL",0 .testfailed: - db "test failed.",$0D,$0A,0 + db " test failed.",$0D,$0A,0 .ok: db "OK!",$0D,$0A,0 @@ -233,9 +233,6 @@ puts: ld a, [hli] ld b, $00 cp b - jr z, .done + ret z call putc jr puts -.done: - ret -