From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Mon, 31 Mar 2008 06:22:45 +0000 (-0400)
Subject: Add CALL (untested) and ROM and internal RAM
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/ef6fbe3130c958177759bd99cf24a6c3edc4693c?ds=sidebyside;hp=69ca9b5f404e06ddf52dc24e40257e3f28aade3d

Add CALL (untested) and ROM and internal RAM
---

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 50f4b03..5ae1765 100644
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
diff --git a/GBZ80Core.v b/GBZ80Core.v
index 338c2d7..cb231c2 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -36,6 +36,7 @@
 `define INSN_NOP				8'b00000000
 `define INSN_RST				8'b11xxx111
 `define INSN_RET				8'b110x1001	// 1 = RETI, 0 = RET
+`define INSN_CALL				8'b11001101
 
 `define INSN_reg_A		3'b111
 `define INSN_reg_B		3'b000
@@ -80,7 +81,7 @@ module GBZ80Core(
 	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
 	reg rd = 1, wr = 0, newcycle = 1;
 	
-	reg [7:0] tmp;					/* Generic temporary reg. */
+	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
 	
 	reg [7:0] buswdata;
 	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
@@ -381,6 +382,34 @@ module GBZ80Core(
 					end
 				endcase
 			end
+			`INSN_CALL: begin
+				case (cycle)
+				0:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				1:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				2:	begin
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+						wdata <= registers[`REG_PCH];
+						wr <= 1;
+					end
+				3:	begin
+						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+						wdata <= registers[`REG_PCL];
+						wr <= 1;
+					end
+				4:	begin /* nothing happens on the bus next cycle! */ end
+				5:	begin
+						`EXEC_NEWCYCLE;	/* do NOT increment the PC */
+					end
+				endcase
+			end
 			default:
 				$stop;
 			endcase
@@ -638,6 +667,34 @@ module GBZ80Core(
 					end
 				endcase
 			end
+			`INSN_CALL: begin
+				case (cycle)
+				0:	cycle <= 1;
+				1:	begin
+						cycle <= 2;
+						tmp <= rdata;	// tmp contains newpcl
+					end
+				2:	begin
+						cycle <= 3;
+						tmp2 <= rdata;	// tmp2 contains newpch
+					end
+				3: begin
+						cycle <= 4;
+						registers[`REG_PCH] <= tmp2;
+					end
+				4: begin
+						cycle <= 5;
+						registers[`REG_PCL] <= tmp;
+					end
+				5: begin
+						{registers[`REG_SPH],registers[`REG_SPL]} <=
+							{registers[`REG_SPH],registers[`REG_SPL]} - 2;
+						cycle <= 0;
+					end
+				endcase
+			end
+			default:
+				$stop;
 			endcase
 			state <= `STATE_FETCH;
 		end
@@ -645,14 +702,53 @@ module GBZ80Core(
 endmodule
 
 `timescale 1ns / 1ps
+module ROM(
+	input [15:0] address,
+	inout [7:0] data,
+	input wr, rd);
+
+	reg [7:0] rom [2047:0];
+	initial $readmemh("rom.hex", rom);
+
+	wire decode = address[15:13] == 0;
+	reg [7:0] odata;
+	wire idata = data;
+	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	
+	always @(wr or rd)
+	begin
+		if (decode && rd)
+			odata <= rom[address];
+	end
+endmodule
+
+module InternalRAM(
+	input [15:0] address,
+	inout [7:0] data,
+	input wr, rd);
+	
+	reg [7:0] ram [8191:0];
+	
+	wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+	reg [7:0] odata;
+	wire idata = data;
+	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	
+	always @(rd or wr)
+	begin
+		if (decode && rd)
+			odata <= ram[address];
+		else if (decode && wr)
+			ram[address] <= idata;
+	end
+endmodule
+
 module TestBench();
 	reg clk = 0;
 	wire [15:0] addr;
 	wire [7:0] data;
 	wire wr, rd;
-	reg [7:0] rom [2047:0];
 	
-	initial $readmemh("rom.hex", rom);
 	always #10 clk <= ~clk;
 	GBZ80Core core(
 		.clk(clk),
@@ -660,5 +756,16 @@ module TestBench();
 		.busdata(data),
 		.buswr(wr),
 		.busrd(rd));
-	assign data = rd ? rom[addr] : 8'bzzzzzzzz;
+	
+	ROM rom(
+		.address(addr),
+		.data(data),
+		.wr(wr),
+		.rd(rd));
+	
+	InternalRAM ram(
+		.address(addr),
+		.data(data),
+		.wr(wr),
+		.rd(rd));
 endmodule