From: Joshua Wise Date: Sat, 19 Apr 2008 07:03:16 +0000 (-0400) Subject: Fix some sync issues? Maybe? X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/ec7274034775dc5e053ff3c96bd141ac50b4fc81?hp=0dea04d38b6864e9734f5a0e556cc088887835bd Fix some sync issues? Maybe? --- diff --git a/LCDC.v b/LCDC.v index 0e1b569..5089129 100644 --- a/LCDC.v +++ b/LCDC.v @@ -19,7 +19,7 @@ module LCDC( output wire lcdcirq, output wire vblankirq, output wire lcdclk, lcdvs, lcdhs, - output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb); + output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb); /***** Needed prototypes *****/ wire [1:0] pixdata; @@ -77,11 +77,12 @@ module LCDC( wire [7:0] vxpos = rSCX + posx - 3; wire [7:0] vypos = rSCY + posy; - assign lcdvs = (posy == 153) && (posx == 455); - assign lcdhs = (posx == 455); - assign lcdr = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000; - assign lcdg = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000; - assign lcdb = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00; + assign lcdvs = (posy == 153) && (posx == 2); + assign lcdhs = (posx == 2); + + wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000; + wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000; + wire [1:0] lcdb_ = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00; reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0; assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq); @@ -118,6 +119,10 @@ module LCDC( end lycirq <= 0; end + + lcdr <= lcdr_; + lcdg <= lcdg_; + lcdb <= lcdb_; end /***** Video RAM *****/ @@ -135,11 +140,12 @@ module LCDC( // The new tile number is loaded when vxpos[2:0] is 3'b110 // The new tile data is loaded when vxpos[2:0] is 3'b111 // The new tile data is latched and ready when vxpos[2:0] is 3'b000! - wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]}; + wire [7:0] vxpos_ = vxpos + 1; + wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]}; reg [7:0] tileno; wire [10:0] tileaddr = {tileno, vypos[2:0]}; reg [7:0] tilehigh, tilelow; - assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]}; + assign pixdata = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]}; wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF); wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF); @@ -148,14 +154,14 @@ module LCDC( wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1]; always @(negedge clk) - if ((vraminuse && ((posx == 1) || (vxpos[2:0] == 3'b110))) || decode_bgmap1) begin + if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin tileno <= bgmap1[bgmapaddr_in]; if (wr && decode_bgmap1 && ~vraminuse) bgmap1[bgmapaddr_in] <= data; end always @(negedge clk) - if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_tiledata) begin + if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin tilehigh <= tiledatahigh[tileaddr_in]; tilelow <= tiledatalow[tileaddr_in]; if (wr && addr[0] && decode_tiledata && ~vraminuse) diff --git a/diag.asm b/diag.asm index 77c5202..c832ff2 100644 --- a/diag.asm +++ b/diag.asm @@ -51,22 +51,22 @@ signon: db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0 tiles: - db %11111111 - db %11111111 - db %11000011 - db %11000011 - db %11000011 - db %11000011 - db %11111111 - db %11111111 - - db %00000000 - db %00000000 - db %00000000 - db %00000000 - db %00000000 - db %00000000 + db %01111100 + db %11000110 + db %11000110 + db %11111110 + db %11000110 + db %11000110 + db %11000110 db %00000000 + + db %11111100 + db %11000110 + db %11000110 + db %11111100 + db %11000110 + db %11000110 + db %11111100 db %00000000 putscreen: