From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 6 Apr 2008 06:26:07 +0000 (-0400)
Subject: Clean up some warnings.
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/eb0f2fe1637a4c6b4532ae08ff7b0af3bf39aef0?ds=inline;hp=81358c71b258a72a2777bba0a0b4a82a7cae298a

Clean up some warnings.
---

diff --git a/GBZ80Core.v b/GBZ80Core.v
index b53a6e2..d556cd5 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -90,9 +90,9 @@
 
 module GBZ80Core(
 	input clk,
-	output reg [15:0] busaddress = 0,	/* BUS_* is latched on STATE_FETCH. */
+	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
-	output reg buswr = 0, output reg busrd = 0,
+	output reg buswr, output reg busrd,
 	input irq, input [7:0] jaddr);
 	
 	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
@@ -112,7 +112,7 @@ module GBZ80Core(
 	reg [7:0] buswdata;
 	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
 	
-	reg ie = 0, iedelay = 0;
+	reg ie, iedelay;
 	
 	initial begin
 		registers[ 0] <= 0;
diff --git a/System.v b/System.v
index 5d4fbed..0afc090 100644
--- a/System.v
+++ b/System.v
@@ -26,7 +26,6 @@ module InternalRAM(
 	
 	wire decode = address[15:13] == 3'b110;
 	reg [7:0] odata;
-	wire idata = data;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
 	always @(negedge clk)
@@ -97,12 +96,11 @@ module CoreTop(
 		.rd(rd));
 	
 	AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-	 .freeze(buttons[0])
-    );
+		.addr(addr), 
+		.clk(clk), 
+		.digit(digits), 
+		.out(seven),
+		.freeze(buttons[0]));
 	 
 	Switches sw(
 		.address(addr),
@@ -115,20 +113,21 @@ module CoreTop(
 		);
 
 	UART nouart (	/* no u */
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+		.clk(clk), 
+		.wr(wr), 
+		.rd(rd), 
+		.addr(addr), 
+		.data(data), 
+		.serial(serio)
+		);
 
-  InternalRAM ram(
+	InternalRAM ram(
 		.address(addr),
 		.data(data),
 		.clk(clk),
 		.wr(wr),
-		.rd(rd));
+		.rd(rd)
+		);
 
 	Timer tmr(
 		.clk(clk),
@@ -136,7 +135,8 @@ module CoreTop(
 		.rd(rd),
 		.addr(addr),
 		.data(data),
-		.irq(tmrirq));
+		.irq(tmrirq)
+		);
 	
 	Interrupt intr(
 		.clk(clk),
diff --git a/Uart.v b/Uart.v
index f87005d..3dd1532 100644
--- a/Uart.v
+++ b/Uart.v
@@ -19,7 +19,6 @@ module UART(
 	reg [7:0] data_stor = 0;
 	reg [15:0] clkdiv = 0;
 	reg have_data = 0;
-	reg data_end = 0;
 	reg [3:0] diqing = 4'b0000;
 	
 	wire new = (wr) && (!have_data) && decode;