From: Christopher Zihao Lu Date: Sun, 11 May 2008 06:44:33 +0000 (-0400) Subject: Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/eaec80f24007825c7abba2affd76f74d520ce4cd?hp=d5f3776614009b3b5232952350cc281d7e0c422f Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy --- diff --git a/CoreTop.prj b/CoreTop.prj index 0df5890..c28c727 100644 --- a/CoreTop.prj +++ b/CoreTop.prj @@ -1,7 +1,7 @@ verilog work "Uart.v" verilog work "Timer.v" verilog work "Interrupt.v" -verilog work "GBZ80Core.v" +verilog work "core/GBZ80Core.v" verilog work "CPUDCM.v" verilog work "7seg.v" verilog work "System.v" @@ -12,3 +12,4 @@ verilog work "Sound1.v" verilog work "Sound2.v" verilog work "Soundcore.v" verilog work "Buttons.v" +verilog work "PS2Button.v" diff --git a/CoreTop.ucf b/CoreTop.ucf index 1981fcd..55b4652 100644 --- a/CoreTop.ucf +++ b/CoreTop.ucf @@ -103,3 +103,5 @@ NET "cr_A<20>" LOC="K3" | SLEW="fast"; NET "cr_A<21>" LOC="D1" | SLEW="fast"; NET "cr_A<22>" LOC="K6" | SLEW="fast"; +NET "ps2c" LOC="R12" | CLOCK_DEDICATED_ROUTE = FALSE; +NET "ps2d" LOC="P11"; \ No newline at end of file diff --git a/Makefile b/Makefile index f42e5b9..732727c 100644 --- a/Makefile +++ b/Makefile @@ -1,14 +1,18 @@ -VLOGS = 7seg.v Framebuffer.v GBZ80Core.v Interrupt.v LCDC.v Sound1.v \ - Sound2.v Soundcore.v System.v Timer.v Uart.v Buttons.v - -VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \ - insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v insn_ret-retcc.v \ - allinsns.v insn_alu8.v insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v \ - insn_ld_reg_imm16.v insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v \ - CPUDCM.v insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \ - insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \ - insn_ldm8_a.v insn_ldm16_a.v insn_ldbcde_a.v insn_alu_ext.v \ - insn_bit.v insn_two_byte.v insn_incdec_reg8.v insn_add_hl.v +VLOGS = 7seg.v Framebuffer.v core/GBZ80Core.v Interrupt.v LCDC.v Sound1.v \ + Sound2.v Soundcore.v System.v Timer.v Uart.v Buttons.v PS2Button.v + +VLOGS_ALL = $(VLOGS) core/insn_call-callcc.v core/insn_incdec16.v \ + core/insn_jr-jrcc.v core/insn_ld_reg_hl.v core/insn_ld_reg_reg.v \ + core/insn_nop.v core/insn_ret-retcc.v core/allinsns.v \ + core/insn_alu8.v core/insn_di-ei.v core/insn_jp_hl.v \ + core/insn_ldh_ac.v core/insn_ld_reg_imm16.v core/insn_ld_sp_hl.v \ + core/insn_pop_reg.v core/insn_rst.v CPUDCM.v core/insn_alu_a.v \ + core/insn_halt.v core/insn_jp-jpcc.v core/insn_ld_hl_reg.v \ + core/insn_ld_reg_imm8.v core/insn_ldx_ahl.v core/insn_push_reg.v \ + core/insn_vop_intr.v core/insn_ldm8_a.v core/insn_ldm16_a.v \ + core/insn_ldbcde_a.v core/insn_alu_ext.v core/insn_bit.v \ + core/insn_two_byte.v core/insn_incdec_reg8.v core/insn_add_hl.v \ + core/insn_add_sp_imm8.v core/insn_ldhl_sp_imm8.v all: CoreTop.svf diff --git a/PS2Button.v b/PS2Button.v index e65226c..81a0e89 100644 --- a/PS2Button.v +++ b/PS2Button.v @@ -1,26 +1,41 @@ module PS2Button( + input clk, input inclk, input indata, - input rst, - output outclk, - output outdata, - output reg [7:0] buttons + output wire [7:0] buttons ); - assign outdata = 1'b1; - assign outclk = 1'b1; - - reg bitcount [3:0] = 0; - reg [7:0] key; - reg keyarrow, keyup, parity; - reg key_a,key_b,key_st,key_sel,key_up,key_dn,key_l,key_r; + reg [3:0] bitcount = 0; + reg [7:0] key = 0; + reg keyarrow = 0, keyup = 0, parity = 0; + reg key_a = 0,key_b = 0,key_st = 0,key_sel = 0,key_up = 0,key_dn = 0,key_l = 0,key_r = 0; assign buttons = {key_st,key_sel,key_b,key_a,key_dn,key_up,key_l,key_r}; + + /* Clock debouncing */ + reg lastinclk = 0; + reg [5:0] debounce = 0; + reg fixedclk = 0; + reg [9:0] resetcountdown = 0; + + always @(posedge clk) begin + if (inclk != lastinclk) begin + lastinclk <= inclk; + debounce <= 1; + resetcountdown <= 10'b1111111111; + end else if (debounce == 0) begin + fixedclk <= inclk; + resetcountdown <= resetcountdown - 1; + end else + debounce <= debounce + 1; + end - always @ (negedge inclk) begin - if(bitcount == 10) begin + always @(negedge fixedclk) begin + if (resetcountdown == 0) + bitcount <= 0; + else if (bitcount == 10) begin bitcount <= 0; - if(parity == (^ key)) begin + if(parity != (^ key)) begin if(keyarrow) begin keyarrow <= 0; case(key) diff --git a/System.v b/System.v index 931e900..02b424c 100644 --- a/System.v +++ b/System.v @@ -114,7 +114,7 @@ module CellularRAM( reg [8:0] rombank = 1; assign cr_nOE = decode ? ~rdlatch : 1; - assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1; + assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1; assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch}; assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} : @@ -232,6 +232,7 @@ module CoreTop( output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, output wire [22:0] cr_A, inout [15:0] cr_DQ, + input ps2c, ps2d, `endif output wire hs, vs, output wire [2:0] r, g, @@ -256,6 +257,7 @@ module CoreTop( IBUFG iclkbuf(.O(xtalb), .I(xtal)); CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk)); pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk)); + wire [7:0] ps2buttons; `endif wire [15:0] addr [1:0]; @@ -348,16 +350,32 @@ module CoreTop( .vgag(g), .vgab(b)); + wire [7:0] sleds; +`ifdef isim + assign leds = sleds; +`else + assign leds = sleds | ps2buttons; +`endif Switches sw( .clk(clk), .address(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), - .ledout(leds), + .ledout(sleds), .switches(switches) ); +`ifdef isim +`else + PS2Button ps2( + .clk(clk), + .inclk(ps2c), + .indata(ps2d), + .buttons(ps2buttons) + ); +`endif + Buttons ass( .core_clk(clk), .addr(addr[0]), @@ -365,7 +383,11 @@ module CoreTop( .wr(wr[0]), .rd(rd[0]), .int(btnirq), + `ifdef isim .buttons(switches) + `else + .buttons(ps2buttons) + `endif ); AddrMon amon( diff --git a/GBZ80Core.v b/core/GBZ80Core.v similarity index 78% rename from GBZ80Core.v rename to core/GBZ80Core.v index 053df4a..fcc3337 100644 --- a/GBZ80Core.v +++ b/core/GBZ80Core.v @@ -40,46 +40,9 @@ `define STATE_EXECUTE 2'h2 `define STATE_WRITEBACK 2'h3 -`define INSN_LD_reg_imm8 9'b000xxx110 -`define INSN_HALT 9'b001110110 -`define INSN_LD_HL_reg 9'b001110xxx -`define INSN_LD_reg_HL 9'b001xxx110 -`define INSN_LD_reg_reg 9'b001xxxxxx -`define INSN_LD_reg_imm16 9'b000xx0001 -`define INSN_LD_SP_HL 9'b011111001 -`define INSN_PUSH_reg 9'b011xx0101 -`define INSN_POP_reg 9'b011xx0001 -`define INSN_LDH_AC 9'b0111x0010 // Either LDH A,(C) or LDH (C),A -`define INSN_LDx_AHL 9'b0001xx010 // LDD/LDI A,(HL) / (HL),A -`define INSN_ALU8 9'b010xxxxxx // 10 xxx yyy -`define INSN_ALU8IMM 9'b011xxx110 -`define INSN_NOP 9'b000000000 -`define INSN_RST 9'b011xxx111 -`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET -`define INSN_RETCC 9'b0110xx000 -`define INSN_CALL 9'b011001101 -`define INSN_CALLCC 9'b0110xx100 // Not that call/cc. -`define INSN_JP_imm 9'b011000011 -`define INSN_JPCC_imm 9'b0110xx010 -`define INSN_ALU_A 9'b000xxx111 -`define INSN_JP_HL 9'b011101001 -`define INSN_JR_imm 9'b000011000 -`define INSN_JRCC_imm 9'b0001xx000 -`define INSN_INCDEC16 9'b000xxx011 `define INSN_VOP_INTR 9'b011111100 // 0xFC is grabbed by the fetch if there is an interrupt pending. -`define INSN_DI 9'b011110011 -`define INSN_EI 9'b011111011 -`define INSN_INCDEC_HL 9'b00011010x -`define INSN_INCDEC_reg8 9'b000xxx10x -`define INSN_LD8M_A 9'b0111x0000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 -`define INSN_LD16M_A 9'b0111x1010 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 -`define INSN_LDBCDE_A 9'b0000xx010 -`define INSN_TWO_BYTE 9'b011001011 // prefix for two-byte opqodes -`define INSN_ALU_EXT 9'b100xxxxxx -`define INSN_BIT 9'b101xxxxxx `define INSN_RES 9'b110xxxxxx `define INSN_SET 9'b111xxxxxx -`define INSN_ADD_HL 9'b000xx1001 `define INSN_cc_NZ 2'b00 `define INSN_cc_Z 2'b01 @@ -110,14 +73,6 @@ `define INSN_alu_XOR 3'b101 `define INSN_alu_OR 3'b110 `define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP? -`define INSN_alu_RLCA 3'b000 -`define INSN_alu_RRCA 3'b001 -`define INSN_alu_RLA 3'b010 -`define INSN_alu_RRA 3'b011 -`define INSN_alu_DAA 3'b100 -`define INSN_alu_CPL 3'b101 -`define INSN_alu_SCF 3'b110 -`define INSN_alu_CCF 3'b111 `define INSN_alu_RLC 3'b000 `define INSN_alu_RRC 3'b001 `define INSN_alu_RL 3'b010 @@ -131,18 +86,13 @@ `define EXEC_NEXTADDR_PCINC address <= `_PC + 1; `define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end `define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end -`ifdef verilator +`ifdef isim `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end `else - `ifdef isim - `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end - `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end - `else -/* Work around XST's retarded bugs :\ */ - `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end - `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end - `endif + /* Work around XST's retarded bugs :\ */ + `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end + `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end `endif module GBZ80Core( diff --git a/allinsns.v b/core/allinsns.v similarity index 93% rename from allinsns.v rename to core/allinsns.v index dfdf04f..4ecd2b1 100644 --- a/allinsns.v +++ b/core/allinsns.v @@ -30,3 +30,5 @@ `include "insn_bit.v" `include "insn_alu_ext.v" `include "insn_add_hl.v" +`include "insn_ldhl_sp_imm8.v" +`include "insn_add_sp_imm8.v" diff --git a/insn_add_hl.v b/core/insn_add_hl.v similarity index 95% rename from insn_add_hl.v rename to core/insn_add_hl.v index 8ff25f4..0d85f95 100644 --- a/insn_add_hl.v +++ b/core/insn_add_hl.v @@ -1,3 +1,5 @@ +`define INSN_ADD_HL 9'b000xx1001 + `ifdef EXECUTE `INSN_ADD_HL: begin case (cycle) diff --git a/core/insn_add_sp_imm8.v b/core/insn_add_sp_imm8.v new file mode 100644 index 0000000..3350bdc --- /dev/null +++ b/core/insn_add_sp_imm8.v @@ -0,0 +1,26 @@ +`define INSN_ADD_SP_IMM8 9'b011101000 + +`ifdef EXECUTE + `INSN_ADD_SP_IMM8: begin + case (cycle) + 0: begin + `EXEC_INC_PC + end + 1: begin + `EXEC_READ(`_PC) + end + 3: begin + `EXEC_NEWCYCLE + `EXEC_INC_PC + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_ADD_SP_IMM8: begin + case (cycle) + 2: `_SP <= `_SP + {rdata[7] ? 8'hFF : 8'h00, rdata}; + endcase + end +`endif diff --git a/insn_alu8.v b/core/insn_alu8.v similarity index 97% rename from insn_alu8.v rename to core/insn_alu8.v index 2921b18..1283a9c 100644 --- a/insn_alu8.v +++ b/core/insn_alu8.v @@ -1,3 +1,6 @@ +`define INSN_ALU8 9'b010xxxxxx // 10 xxx yyy +`define INSN_ALU8IMM 9'b011xxx110 + `ifdef EXECUTE `INSN_ALU8,`INSN_ALU8IMM: begin if ((opcode[7:6] == 2'b11) && (cycle == 0)) begin // alu8imm diff --git a/insn_alu_a.v b/core/insn_alu_a.v similarity index 73% rename from insn_alu_a.v rename to core/insn_alu_a.v index 57a74fc..14ccd76 100644 --- a/insn_alu_a.v +++ b/core/insn_alu_a.v @@ -1,3 +1,14 @@ +`define INSN_alu_RLCA 3'b000 +`define INSN_alu_RRCA 3'b001 +`define INSN_alu_RLA 3'b010 +`define INSN_alu_RRA 3'b011 +`define INSN_alu_DAA 3'b100 +`define INSN_alu_CPL 3'b101 +`define INSN_alu_SCF 3'b110 +`define INSN_alu_CCF 3'b111 + +`define INSN_ALU_A 9'b000xxx111 + `ifdef EXECUTE `INSN_ALU_A: begin `EXEC_NEWCYCLE diff --git a/insn_alu_ext.v b/core/insn_alu_ext.v similarity index 94% rename from insn_alu_ext.v rename to core/insn_alu_ext.v index 1b7825b..b4046e8 100644 --- a/insn_alu_ext.v +++ b/core/insn_alu_ext.v @@ -1,3 +1,5 @@ +`define INSN_ALU_EXT 9'b100xxxxxx + `ifdef EXECUTE `INSN_ALU_EXT: begin if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) @@ -24,6 +26,7 @@ if(cycle == 0) begin end else if(cycle == 1) begin `EXEC_WRITE(`_HL, alu_res) + `_F <= {f_res,`_F[3:0]}; end else begin `EXEC_NEWCYCLE end diff --git a/insn_bit.v b/core/insn_bit.v similarity index 95% rename from insn_bit.v rename to core/insn_bit.v index 379215e..ca50e58 100644 --- a/insn_bit.v +++ b/core/insn_bit.v @@ -1,3 +1,5 @@ +`define INSN_BIT 9'b101xxxxxx + `ifdef EXECUTE `INSN_BIT: begin if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin diff --git a/insn_call-callcc.v b/core/insn_call-callcc.v similarity index 91% rename from insn_call-callcc.v rename to core/insn_call-callcc.v index a446a3d..85cea27 100644 --- a/insn_call-callcc.v +++ b/core/insn_call-callcc.v @@ -1,3 +1,6 @@ +`define INSN_CALL 9'b011001101 +`define INSN_CALLCC 9'b0110xx100 // Not that call/cc. + `ifdef EXECUTE `INSN_CALL,`INSN_CALLCC: begin case (cycle) diff --git a/insn_di-ei.v b/core/insn_di-ei.v similarity index 71% rename from insn_di-ei.v rename to core/insn_di-ei.v index eff1de2..6e65ceb 100644 --- a/insn_di-ei.v +++ b/core/insn_di-ei.v @@ -1,3 +1,6 @@ +`define INSN_DI 9'b011110011 +`define INSN_EI 9'b011111011 + `ifdef EXECUTE `INSN_DI,`INSN_EI: begin `EXEC_NEWCYCLE diff --git a/insn_halt.v b/core/insn_halt.v similarity index 87% rename from insn_halt.v rename to core/insn_halt.v index 4d2573f..9a3c1c0 100644 --- a/insn_halt.v +++ b/core/insn_halt.v @@ -1,3 +1,5 @@ +`define INSN_HALT 9'b001110110 + `ifdef EXECUTE `INSN_HALT: begin `EXEC_NEWCYCLE diff --git a/insn_incdec16.v b/core/insn_incdec16.v similarity index 94% rename from insn_incdec16.v rename to core/insn_incdec16.v index 95e0d38..1489779 100644 --- a/insn_incdec16.v +++ b/core/insn_incdec16.v @@ -1,3 +1,5 @@ +`define INSN_INCDEC16 9'b000xxx011 + `ifdef EXECUTE `INSN_INCDEC16: begin case (cycle) diff --git a/insn_incdec_hl.v b/core/insn_incdec_hl.v similarity index 88% rename from insn_incdec_hl.v rename to core/insn_incdec_hl.v index abfe495..1406fd8 100644 --- a/insn_incdec_hl.v +++ b/core/insn_incdec_hl.v @@ -1,3 +1,5 @@ +`define INSN_INCDEC_HL 9'b00011010x + `ifdef EXECUTE `INSN_INCDEC_HL: begin case (cycle) diff --git a/insn_incdec_reg8.v b/core/insn_incdec_reg8.v similarity index 96% rename from insn_incdec_reg8.v rename to core/insn_incdec_reg8.v index 58582b6..e89ceba 100644 --- a/insn_incdec_reg8.v +++ b/core/insn_incdec_reg8.v @@ -1,3 +1,5 @@ +`define INSN_INCDEC_reg8 9'b000xxx10x + `ifdef EXECUTE `INSN_INCDEC_reg8: begin `EXEC_INC_PC diff --git a/insn_jp-jpcc.v b/core/insn_jp-jpcc.v similarity index 92% rename from insn_jp-jpcc.v rename to core/insn_jp-jpcc.v index 7c8fb22..c54043d 100644 --- a/insn_jp-jpcc.v +++ b/core/insn_jp-jpcc.v @@ -1,3 +1,6 @@ +`define INSN_JP_imm 9'b011000011 +`define INSN_JPCC_imm 9'b0110xx010 + `ifdef EXECUTE `INSN_JP_imm,`INSN_JPCC_imm: begin case (cycle) diff --git a/insn_jp_hl.v b/core/insn_jp_hl.v similarity index 75% rename from insn_jp_hl.v rename to core/insn_jp_hl.v index 4aa9a41..707f62c 100644 --- a/insn_jp_hl.v +++ b/core/insn_jp_hl.v @@ -1,3 +1,5 @@ +`define INSN_JP_HL 9'b011101001 + `ifdef EXECUTE `INSN_JP_HL: `EXEC_NEWCYCLE `endif diff --git a/insn_jr-jrcc.v b/core/insn_jr-jrcc.v similarity index 90% rename from insn_jr-jrcc.v rename to core/insn_jr-jrcc.v index 767db6a..a2c5f7e 100644 --- a/insn_jr-jrcc.v +++ b/core/insn_jr-jrcc.v @@ -1,3 +1,6 @@ +`define INSN_JR_imm 9'b000011000 +`define INSN_JRCC_imm 9'b0001xx000 + `ifdef EXECUTE `INSN_JR_imm,`INSN_JRCC_imm: begin case (cycle) diff --git a/insn_ld_hl_reg.v b/core/insn_ld_hl_reg.v similarity index 93% rename from insn_ld_hl_reg.v rename to core/insn_ld_hl_reg.v index fdf3d9b..974584f 100644 --- a/insn_ld_hl_reg.v +++ b/core/insn_ld_hl_reg.v @@ -1,3 +1,5 @@ +`define INSN_LD_HL_reg 9'b001110xxx + `ifdef EXECUTE `INSN_LD_HL_reg: begin case (cycle) diff --git a/insn_ld_reg_hl.v b/core/insn_ld_reg_hl.v similarity index 92% rename from insn_ld_reg_hl.v rename to core/insn_ld_reg_hl.v index e420f2f..f6a67c7 100644 --- a/insn_ld_reg_hl.v +++ b/core/insn_ld_reg_hl.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_HL 9'b001xxx110 + `ifdef EXECUTE `INSN_LD_reg_HL: begin case(cycle) diff --git a/insn_ld_reg_imm16.v b/core/insn_ld_reg_imm16.v similarity index 94% rename from insn_ld_reg_imm16.v rename to core/insn_ld_reg_imm16.v index cf79aaa..3784fbf 100644 --- a/insn_ld_reg_imm16.v +++ b/core/insn_ld_reg_imm16.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_imm16 9'b000xx0001 + `ifdef EXECUTE `INSN_LD_reg_imm16: begin `EXEC_INC_PC diff --git a/insn_ld_reg_imm8.v b/core/insn_ld_reg_imm8.v similarity index 95% rename from insn_ld_reg_imm8.v rename to core/insn_ld_reg_imm8.v index 7340421..b1deb9c 100644 --- a/insn_ld_reg_imm8.v +++ b/core/insn_ld_reg_imm8.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_imm8 9'b000xxx110 + `ifdef EXECUTE `INSN_LD_reg_imm8: begin case (cycle) diff --git a/insn_ld_reg_reg.v b/core/insn_ld_reg_reg.v similarity index 93% rename from insn_ld_reg_reg.v rename to core/insn_ld_reg_reg.v index 7bbea95..e0d72e7 100644 --- a/insn_ld_reg_reg.v +++ b/core/insn_ld_reg_reg.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_reg 9'b001xxxxxx + `ifdef EXECUTE `INSN_LD_reg_reg: begin `EXEC_INC_PC diff --git a/insn_ld_sp_hl.v b/core/insn_ld_sp_hl.v similarity index 88% rename from insn_ld_sp_hl.v rename to core/insn_ld_sp_hl.v index 3d4fc18..55546f8 100644 --- a/insn_ld_sp_hl.v +++ b/core/insn_ld_sp_hl.v @@ -1,3 +1,5 @@ +`define INSN_LD_SP_HL 9'b011111001 + `ifdef EXECUTE `INSN_LD_SP_HL: begin case (cycle) diff --git a/insn_ldbcde_a.v b/core/insn_ldbcde_a.v similarity index 92% rename from insn_ldbcde_a.v rename to core/insn_ldbcde_a.v index 2a91dc6..5ce0ee1 100644 --- a/insn_ldbcde_a.v +++ b/core/insn_ldbcde_a.v @@ -1,3 +1,5 @@ +`define INSN_LDBCDE_A 9'b0000xx010 + `ifdef EXECUTE `INSN_LDBCDE_A: begin case (cycle) diff --git a/insn_ldh_ac.v b/core/insn_ldh_ac.v similarity index 84% rename from insn_ldh_ac.v rename to core/insn_ldh_ac.v index a2ff5cc..30918e5 100644 --- a/insn_ldh_ac.v +++ b/core/insn_ldh_ac.v @@ -1,3 +1,5 @@ +`define INSN_LDH_AC 9'b0111x0010 // Either LDH A,(C) or LDH (C),A + `ifdef EXECUTE `INSN_LDH_AC: begin case (cycle) diff --git a/core/insn_ldhl_sp_imm8.v b/core/insn_ldhl_sp_imm8.v new file mode 100644 index 0000000..688465a --- /dev/null +++ b/core/insn_ldhl_sp_imm8.v @@ -0,0 +1,26 @@ +`define INSN_LDHL_SP_IMM8 9'b011111000 + +`ifdef EXECUTE + `INSN_LDHL_SP_IMM8: begin + case (cycle) + 0: begin + `EXEC_INC_PC + end + 1: begin + `EXEC_READ(`_PC) + end + 2: begin + `EXEC_NEWCYCLE + `EXEC_INC_PC + end + endcase + end +`endif + +`ifdef WRITEBACK + `INSN_LDHL_SP_IMM8: begin + case (cycle) + 2: `_HL <= `_SP + {rdata[7] ? 8'hFF : 8'h00, rdata}; + endcase + end +`endif diff --git a/insn_ldm16_a.v b/core/insn_ldm16_a.v similarity index 86% rename from insn_ldm16_a.v rename to core/insn_ldm16_a.v index d8356f7..744551e 100644 --- a/insn_ldm16_a.v +++ b/core/insn_ldm16_a.v @@ -1,3 +1,5 @@ +`define INSN_LD16M_A 9'b0111x1010 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 + // If opcode[4], then ld A, x, else ld x, A // If opcode[1], then ld 16m8, else ld 8m8 diff --git a/insn_ldm8_a.v b/core/insn_ldm8_a.v similarity index 83% rename from insn_ldm8_a.v rename to core/insn_ldm8_a.v index 14d82ca..8a5ffa4 100644 --- a/insn_ldm8_a.v +++ b/core/insn_ldm8_a.v @@ -1,3 +1,5 @@ +`define INSN_LD8M_A 9'b0111x0000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 + // If opcode[4], then ld A, x, else ld x, A // If opcode[1], then ld 16m8, else ld 8m8 diff --git a/insn_ldx_ahl.v b/core/insn_ldx_ahl.v similarity index 88% rename from insn_ldx_ahl.v rename to core/insn_ldx_ahl.v index a2d2420..55a8f21 100644 --- a/insn_ldx_ahl.v +++ b/core/insn_ldx_ahl.v @@ -1,3 +1,5 @@ +`define INSN_LDx_AHL 9'b0001xx010 // LDD/LDI A,(HL) / (HL),A + `ifdef EXECUTE `INSN_LDx_AHL: begin case (cycle) diff --git a/insn_nop.v b/core/insn_nop.v similarity index 79% rename from insn_nop.v rename to core/insn_nop.v index 9270c88..d8ba833 100644 --- a/insn_nop.v +++ b/core/insn_nop.v @@ -1,3 +1,5 @@ +`define INSN_NOP 9'b000000000 + `ifdef EXECUTE `INSN_NOP: begin `EXEC_NEWCYCLE diff --git a/insn_pop_reg.v b/core/insn_pop_reg.v similarity index 95% rename from insn_pop_reg.v rename to core/insn_pop_reg.v index 5a7da08..55d12ec 100644 --- a/insn_pop_reg.v +++ b/core/insn_pop_reg.v @@ -1,3 +1,5 @@ +`define INSN_POP_reg 9'b011xx0001 + `ifdef EXECUTE `INSN_POP_reg: begin /* POP is 12 cycles! */ case (cycle) diff --git a/insn_push_reg.v b/core/insn_push_reg.v similarity index 95% rename from insn_push_reg.v rename to core/insn_push_reg.v index 6b789e5..0c3692a 100644 --- a/insn_push_reg.v +++ b/core/insn_push_reg.v @@ -1,3 +1,5 @@ +`define INSN_PUSH_reg 9'b011xx0101 + `ifdef EXECUTE `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */ case (cycle) diff --git a/insn_ret-retcc.v b/core/insn_ret-retcc.v similarity index 91% rename from insn_ret-retcc.v rename to core/insn_ret-retcc.v index dab27c3..4ad962e 100644 --- a/insn_ret-retcc.v +++ b/core/insn_ret-retcc.v @@ -1,3 +1,6 @@ +`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET +`define INSN_RETCC 9'b0110xx000 + `ifdef EXECUTE `INSN_RET,`INSN_RETCC: begin case (cycle) diff --git a/insn_rst.v b/core/insn_rst.v similarity index 93% rename from insn_rst.v rename to core/insn_rst.v index 4b65032..8ec0421 100644 --- a/insn_rst.v +++ b/core/insn_rst.v @@ -1,3 +1,5 @@ +`define INSN_RST 9'b011xxx111 + `ifdef EXECUTE `INSN_RST: begin case (cycle) diff --git a/core/insn_two_byte.v b/core/insn_two_byte.v new file mode 100644 index 0000000..7a51cbc --- /dev/null +++ b/core/insn_two_byte.v @@ -0,0 +1,13 @@ +`define INSN_TWO_BYTE 9'b011001011 // prefix for two-byte opqodes + +`ifdef EXECUTE + `INSN_TWO_BYTE: begin + `EXEC_INC_PC + `EXEC_NEWCYCLE_TWOBYTE + end +`endif + +`ifdef WRITEBACK + `INSN_TWO_BYTE: begin + end +`endif diff --git a/insn_vop_intr.v b/core/insn_vop_intr.v similarity index 100% rename from insn_vop_intr.v rename to core/insn_vop_intr.v diff --git a/opcodes b/opcodes index 451a6b6..8aa627e 100644 --- a/opcodes +++ b/opcodes @@ -11,8 +11,6 @@ bits insn notes 0001 0000 STOP 0111 0110 HALT Danger! Helvetica! 1100 1011 - - - see two-byte opcodes below -1110 1000 ADD SP, imm8 -1111 1000 LDHL SP, imm8 load SP+n (signed n) into HL *****************************