From: Joshua Wise Date: Sat, 10 May 2008 07:41:06 +0000 (-0400) Subject: Move macro defines out to files X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/e7fe9dc201afb96f401fb2d3cf5aa19aa7e8e796?ds=sidebyside Move macro defines out to files --- diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v index 053df4a..fcc3337 100644 --- a/core/GBZ80Core.v +++ b/core/GBZ80Core.v @@ -40,46 +40,9 @@ `define STATE_EXECUTE 2'h2 `define STATE_WRITEBACK 2'h3 -`define INSN_LD_reg_imm8 9'b000xxx110 -`define INSN_HALT 9'b001110110 -`define INSN_LD_HL_reg 9'b001110xxx -`define INSN_LD_reg_HL 9'b001xxx110 -`define INSN_LD_reg_reg 9'b001xxxxxx -`define INSN_LD_reg_imm16 9'b000xx0001 -`define INSN_LD_SP_HL 9'b011111001 -`define INSN_PUSH_reg 9'b011xx0101 -`define INSN_POP_reg 9'b011xx0001 -`define INSN_LDH_AC 9'b0111x0010 // Either LDH A,(C) or LDH (C),A -`define INSN_LDx_AHL 9'b0001xx010 // LDD/LDI A,(HL) / (HL),A -`define INSN_ALU8 9'b010xxxxxx // 10 xxx yyy -`define INSN_ALU8IMM 9'b011xxx110 -`define INSN_NOP 9'b000000000 -`define INSN_RST 9'b011xxx111 -`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET -`define INSN_RETCC 9'b0110xx000 -`define INSN_CALL 9'b011001101 -`define INSN_CALLCC 9'b0110xx100 // Not that call/cc. -`define INSN_JP_imm 9'b011000011 -`define INSN_JPCC_imm 9'b0110xx010 -`define INSN_ALU_A 9'b000xxx111 -`define INSN_JP_HL 9'b011101001 -`define INSN_JR_imm 9'b000011000 -`define INSN_JRCC_imm 9'b0001xx000 -`define INSN_INCDEC16 9'b000xxx011 `define INSN_VOP_INTR 9'b011111100 // 0xFC is grabbed by the fetch if there is an interrupt pending. -`define INSN_DI 9'b011110011 -`define INSN_EI 9'b011111011 -`define INSN_INCDEC_HL 9'b00011010x -`define INSN_INCDEC_reg8 9'b000xxx10x -`define INSN_LD8M_A 9'b0111x0000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 -`define INSN_LD16M_A 9'b0111x1010 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 -`define INSN_LDBCDE_A 9'b0000xx010 -`define INSN_TWO_BYTE 9'b011001011 // prefix for two-byte opqodes -`define INSN_ALU_EXT 9'b100xxxxxx -`define INSN_BIT 9'b101xxxxxx `define INSN_RES 9'b110xxxxxx `define INSN_SET 9'b111xxxxxx -`define INSN_ADD_HL 9'b000xx1001 `define INSN_cc_NZ 2'b00 `define INSN_cc_Z 2'b01 @@ -110,14 +73,6 @@ `define INSN_alu_XOR 3'b101 `define INSN_alu_OR 3'b110 `define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP? -`define INSN_alu_RLCA 3'b000 -`define INSN_alu_RRCA 3'b001 -`define INSN_alu_RLA 3'b010 -`define INSN_alu_RRA 3'b011 -`define INSN_alu_DAA 3'b100 -`define INSN_alu_CPL 3'b101 -`define INSN_alu_SCF 3'b110 -`define INSN_alu_CCF 3'b111 `define INSN_alu_RLC 3'b000 `define INSN_alu_RRC 3'b001 `define INSN_alu_RL 3'b010 @@ -131,18 +86,13 @@ `define EXEC_NEXTADDR_PCINC address <= `_PC + 1; `define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end `define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end -`ifdef verilator +`ifdef isim `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end `else - `ifdef isim - `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end - `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end - `else -/* Work around XST's retarded bugs :\ */ - `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end - `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end - `endif + /* Work around XST's retarded bugs :\ */ + `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end + `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end `endif module GBZ80Core( diff --git a/core/insn_add_hl.v b/core/insn_add_hl.v index 8ff25f4..0d85f95 100644 --- a/core/insn_add_hl.v +++ b/core/insn_add_hl.v @@ -1,3 +1,5 @@ +`define INSN_ADD_HL 9'b000xx1001 + `ifdef EXECUTE `INSN_ADD_HL: begin case (cycle) diff --git a/core/insn_alu8.v b/core/insn_alu8.v index 2921b18..1283a9c 100644 --- a/core/insn_alu8.v +++ b/core/insn_alu8.v @@ -1,3 +1,6 @@ +`define INSN_ALU8 9'b010xxxxxx // 10 xxx yyy +`define INSN_ALU8IMM 9'b011xxx110 + `ifdef EXECUTE `INSN_ALU8,`INSN_ALU8IMM: begin if ((opcode[7:6] == 2'b11) && (cycle == 0)) begin // alu8imm diff --git a/core/insn_alu_a.v b/core/insn_alu_a.v index 57a74fc..14ccd76 100644 --- a/core/insn_alu_a.v +++ b/core/insn_alu_a.v @@ -1,3 +1,14 @@ +`define INSN_alu_RLCA 3'b000 +`define INSN_alu_RRCA 3'b001 +`define INSN_alu_RLA 3'b010 +`define INSN_alu_RRA 3'b011 +`define INSN_alu_DAA 3'b100 +`define INSN_alu_CPL 3'b101 +`define INSN_alu_SCF 3'b110 +`define INSN_alu_CCF 3'b111 + +`define INSN_ALU_A 9'b000xxx111 + `ifdef EXECUTE `INSN_ALU_A: begin `EXEC_NEWCYCLE diff --git a/core/insn_alu_ext.v b/core/insn_alu_ext.v index 1b7825b..b4046e8 100644 --- a/core/insn_alu_ext.v +++ b/core/insn_alu_ext.v @@ -1,3 +1,5 @@ +`define INSN_ALU_EXT 9'b100xxxxxx + `ifdef EXECUTE `INSN_ALU_EXT: begin if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) @@ -24,6 +26,7 @@ if(cycle == 0) begin end else if(cycle == 1) begin `EXEC_WRITE(`_HL, alu_res) + `_F <= {f_res,`_F[3:0]}; end else begin `EXEC_NEWCYCLE end diff --git a/core/insn_bit.v b/core/insn_bit.v index 379215e..ca50e58 100644 --- a/core/insn_bit.v +++ b/core/insn_bit.v @@ -1,3 +1,5 @@ +`define INSN_BIT 9'b101xxxxxx + `ifdef EXECUTE `INSN_BIT: begin if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin diff --git a/core/insn_call-callcc.v b/core/insn_call-callcc.v index a446a3d..85cea27 100644 --- a/core/insn_call-callcc.v +++ b/core/insn_call-callcc.v @@ -1,3 +1,6 @@ +`define INSN_CALL 9'b011001101 +`define INSN_CALLCC 9'b0110xx100 // Not that call/cc. + `ifdef EXECUTE `INSN_CALL,`INSN_CALLCC: begin case (cycle) diff --git a/core/insn_di-ei.v b/core/insn_di-ei.v index eff1de2..6e65ceb 100644 --- a/core/insn_di-ei.v +++ b/core/insn_di-ei.v @@ -1,3 +1,6 @@ +`define INSN_DI 9'b011110011 +`define INSN_EI 9'b011111011 + `ifdef EXECUTE `INSN_DI,`INSN_EI: begin `EXEC_NEWCYCLE diff --git a/core/insn_halt.v b/core/insn_halt.v index 4d2573f..9a3c1c0 100644 --- a/core/insn_halt.v +++ b/core/insn_halt.v @@ -1,3 +1,5 @@ +`define INSN_HALT 9'b001110110 + `ifdef EXECUTE `INSN_HALT: begin `EXEC_NEWCYCLE diff --git a/core/insn_incdec16.v b/core/insn_incdec16.v index 95e0d38..1489779 100644 --- a/core/insn_incdec16.v +++ b/core/insn_incdec16.v @@ -1,3 +1,5 @@ +`define INSN_INCDEC16 9'b000xxx011 + `ifdef EXECUTE `INSN_INCDEC16: begin case (cycle) diff --git a/core/insn_incdec_hl.v b/core/insn_incdec_hl.v index abfe495..1406fd8 100644 --- a/core/insn_incdec_hl.v +++ b/core/insn_incdec_hl.v @@ -1,3 +1,5 @@ +`define INSN_INCDEC_HL 9'b00011010x + `ifdef EXECUTE `INSN_INCDEC_HL: begin case (cycle) diff --git a/core/insn_incdec_reg8.v b/core/insn_incdec_reg8.v index 58582b6..e89ceba 100644 --- a/core/insn_incdec_reg8.v +++ b/core/insn_incdec_reg8.v @@ -1,3 +1,5 @@ +`define INSN_INCDEC_reg8 9'b000xxx10x + `ifdef EXECUTE `INSN_INCDEC_reg8: begin `EXEC_INC_PC diff --git a/core/insn_jp-jpcc.v b/core/insn_jp-jpcc.v index 7c8fb22..c54043d 100644 --- a/core/insn_jp-jpcc.v +++ b/core/insn_jp-jpcc.v @@ -1,3 +1,6 @@ +`define INSN_JP_imm 9'b011000011 +`define INSN_JPCC_imm 9'b0110xx010 + `ifdef EXECUTE `INSN_JP_imm,`INSN_JPCC_imm: begin case (cycle) diff --git a/core/insn_jp_hl.v b/core/insn_jp_hl.v index 4aa9a41..707f62c 100644 --- a/core/insn_jp_hl.v +++ b/core/insn_jp_hl.v @@ -1,3 +1,5 @@ +`define INSN_JP_HL 9'b011101001 + `ifdef EXECUTE `INSN_JP_HL: `EXEC_NEWCYCLE `endif diff --git a/core/insn_jr-jrcc.v b/core/insn_jr-jrcc.v index 767db6a..a2c5f7e 100644 --- a/core/insn_jr-jrcc.v +++ b/core/insn_jr-jrcc.v @@ -1,3 +1,6 @@ +`define INSN_JR_imm 9'b000011000 +`define INSN_JRCC_imm 9'b0001xx000 + `ifdef EXECUTE `INSN_JR_imm,`INSN_JRCC_imm: begin case (cycle) diff --git a/core/insn_ld_hl_reg.v b/core/insn_ld_hl_reg.v index fdf3d9b..974584f 100644 --- a/core/insn_ld_hl_reg.v +++ b/core/insn_ld_hl_reg.v @@ -1,3 +1,5 @@ +`define INSN_LD_HL_reg 9'b001110xxx + `ifdef EXECUTE `INSN_LD_HL_reg: begin case (cycle) diff --git a/core/insn_ld_reg_hl.v b/core/insn_ld_reg_hl.v index e420f2f..f6a67c7 100644 --- a/core/insn_ld_reg_hl.v +++ b/core/insn_ld_reg_hl.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_HL 9'b001xxx110 + `ifdef EXECUTE `INSN_LD_reg_HL: begin case(cycle) diff --git a/core/insn_ld_reg_imm16.v b/core/insn_ld_reg_imm16.v index cf79aaa..3784fbf 100644 --- a/core/insn_ld_reg_imm16.v +++ b/core/insn_ld_reg_imm16.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_imm16 9'b000xx0001 + `ifdef EXECUTE `INSN_LD_reg_imm16: begin `EXEC_INC_PC diff --git a/core/insn_ld_reg_imm8.v b/core/insn_ld_reg_imm8.v index 7340421..b1deb9c 100644 --- a/core/insn_ld_reg_imm8.v +++ b/core/insn_ld_reg_imm8.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_imm8 9'b000xxx110 + `ifdef EXECUTE `INSN_LD_reg_imm8: begin case (cycle) diff --git a/core/insn_ld_reg_reg.v b/core/insn_ld_reg_reg.v index 7bbea95..e0d72e7 100644 --- a/core/insn_ld_reg_reg.v +++ b/core/insn_ld_reg_reg.v @@ -1,3 +1,5 @@ +`define INSN_LD_reg_reg 9'b001xxxxxx + `ifdef EXECUTE `INSN_LD_reg_reg: begin `EXEC_INC_PC diff --git a/core/insn_ld_sp_hl.v b/core/insn_ld_sp_hl.v index 3d4fc18..55546f8 100644 --- a/core/insn_ld_sp_hl.v +++ b/core/insn_ld_sp_hl.v @@ -1,3 +1,5 @@ +`define INSN_LD_SP_HL 9'b011111001 + `ifdef EXECUTE `INSN_LD_SP_HL: begin case (cycle) diff --git a/core/insn_ldbcde_a.v b/core/insn_ldbcde_a.v index 2a91dc6..5ce0ee1 100644 --- a/core/insn_ldbcde_a.v +++ b/core/insn_ldbcde_a.v @@ -1,3 +1,5 @@ +`define INSN_LDBCDE_A 9'b0000xx010 + `ifdef EXECUTE `INSN_LDBCDE_A: begin case (cycle) diff --git a/core/insn_ldh_ac.v b/core/insn_ldh_ac.v index a2ff5cc..30918e5 100644 --- a/core/insn_ldh_ac.v +++ b/core/insn_ldh_ac.v @@ -1,3 +1,5 @@ +`define INSN_LDH_AC 9'b0111x0010 // Either LDH A,(C) or LDH (C),A + `ifdef EXECUTE `INSN_LDH_AC: begin case (cycle) diff --git a/core/insn_ldm16_a.v b/core/insn_ldm16_a.v index d8356f7..744551e 100644 --- a/core/insn_ldm16_a.v +++ b/core/insn_ldm16_a.v @@ -1,3 +1,5 @@ +`define INSN_LD16M_A 9'b0111x1010 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 + // If opcode[4], then ld A, x, else ld x, A // If opcode[1], then ld 16m8, else ld 8m8 diff --git a/core/insn_ldm8_a.v b/core/insn_ldm8_a.v index 14d82ca..8a5ffa4 100644 --- a/core/insn_ldm8_a.v +++ b/core/insn_ldm8_a.v @@ -1,3 +1,5 @@ +`define INSN_LD8M_A 9'b0111x0000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8 + // If opcode[4], then ld A, x, else ld x, A // If opcode[1], then ld 16m8, else ld 8m8 diff --git a/core/insn_ldx_ahl.v b/core/insn_ldx_ahl.v index a2d2420..55a8f21 100644 --- a/core/insn_ldx_ahl.v +++ b/core/insn_ldx_ahl.v @@ -1,3 +1,5 @@ +`define INSN_LDx_AHL 9'b0001xx010 // LDD/LDI A,(HL) / (HL),A + `ifdef EXECUTE `INSN_LDx_AHL: begin case (cycle) diff --git a/core/insn_nop.v b/core/insn_nop.v index 9270c88..d8ba833 100644 --- a/core/insn_nop.v +++ b/core/insn_nop.v @@ -1,3 +1,5 @@ +`define INSN_NOP 9'b000000000 + `ifdef EXECUTE `INSN_NOP: begin `EXEC_NEWCYCLE diff --git a/core/insn_pop_reg.v b/core/insn_pop_reg.v index 5a7da08..55d12ec 100644 --- a/core/insn_pop_reg.v +++ b/core/insn_pop_reg.v @@ -1,3 +1,5 @@ +`define INSN_POP_reg 9'b011xx0001 + `ifdef EXECUTE `INSN_POP_reg: begin /* POP is 12 cycles! */ case (cycle) diff --git a/core/insn_push_reg.v b/core/insn_push_reg.v index 6b789e5..0c3692a 100644 --- a/core/insn_push_reg.v +++ b/core/insn_push_reg.v @@ -1,3 +1,5 @@ +`define INSN_PUSH_reg 9'b011xx0101 + `ifdef EXECUTE `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */ case (cycle) diff --git a/core/insn_ret-retcc.v b/core/insn_ret-retcc.v index dab27c3..4ad962e 100644 --- a/core/insn_ret-retcc.v +++ b/core/insn_ret-retcc.v @@ -1,3 +1,6 @@ +`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET +`define INSN_RETCC 9'b0110xx000 + `ifdef EXECUTE `INSN_RET,`INSN_RETCC: begin case (cycle) diff --git a/core/insn_rst.v b/core/insn_rst.v index 4b65032..8ec0421 100644 --- a/core/insn_rst.v +++ b/core/insn_rst.v @@ -1,3 +1,5 @@ +`define INSN_RST 9'b011xxx111 + `ifdef EXECUTE `INSN_RST: begin case (cycle) diff --git a/core/insn_two_byte.v b/core/insn_two_byte.v index 78cd7c7..7a51cbc 100644 --- a/core/insn_two_byte.v +++ b/core/insn_two_byte.v @@ -1,3 +1,5 @@ +`define INSN_TWO_BYTE 9'b011001011 // prefix for two-byte opqodes + `ifdef EXECUTE `INSN_TWO_BYTE: begin `EXEC_INC_PC