From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 3 May 2008 05:21:08 +0000 (-0400)
Subject: Add some verilator and isim compatibility
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/e7fb589a21ee26ad897e03cbd0d7a647d9cd97e5?hp=75ab1e9975f64989ee18450eb09b66b33ec5def8
Add some verilator and isim compatibility
---
diff --git a/GBZ80Core.v b/GBZ80Core.v
index 05c449a..1182b32 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -130,8 +130,19 @@
`define EXEC_NEXTADDR_PCINC address <= `_PC + 1;
`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end
`define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
-`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
-`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
+`ifdef verilator
+ `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end
+ `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end
+`else
+ `ifdef isim
+ `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end
+ `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end
+ `else
+/* Work around XST's retarded bugs :\ */
+ `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
+ `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
+ `endif
+`endif
module GBZ80Core(
input clk,
@@ -185,7 +196,7 @@ module GBZ80Core(
2'b0,
tmp[0]};
- assign sla = {tmp[6:0],0};
+ assign sla = {tmp[6:0],1'b0};
assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
2'b0,
tmp[7]};
@@ -194,10 +205,10 @@ module GBZ80Core(
// assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf =
assign swap = {tmp[3:0],tmp[7:4]};
- assign swapf = {(tmp == 0 ? 1'b1 : 1'b0),
+ assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
3'b0};
- assign srl = {0,tmp[7:1]};
+ assign srl = {1'b0,tmp[7:1]};
assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
2'b0,
tmp[0]};
@@ -267,12 +278,12 @@ module GBZ80Core(
`STATE_DECODE: begin
if (newcycle) begin
if (twobyte) begin
- opcode <= {1,busdata};
+ opcode <= {1'b1,busdata};
twobyte <= 0;
end else if (ie && irq)
opcode <= `INSN_VOP_INTR;
else
- opcode <= {0,busdata};
+ opcode <= {1'b0,busdata};
rdata <= busdata;
newcycle <= 0;
cycle <= 0;
diff --git a/System.v b/System.v
index dc70cc0..cdcee09 100644
--- a/System.v
+++ b/System.v
@@ -83,7 +83,16 @@ module Switches(
end
endmodule
+`ifdef isim
+module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
+endmodule
+`endif
+
module CoreTop(
+`ifdef isim
+ output reg vgaclk = 0,
+ output reg clk = 0,
+`else
input xtal,
input [7:0] switches,
input [3:0] buttons,
@@ -91,16 +100,31 @@ module CoreTop(
output serio,
output wire [3:0] digits,
output wire [7:0] seven,
+`endif
output wire hs, vs,
output wire [2:0] r, g,
output wire [1:0] b,
output wire soundl, soundr);
+
+`ifdef isim
+ always #62 clk <= ~clk;
+ always #100 vgaclk <= ~vgaclk;
+
+ Dumpable dump(r,g,b,hs,vs,vgaclk);
+ wire [7:0] leds;
+ wire serio;
+ wire [3:0] digits;
+ wire [7:0] seven;
+ wire [7:0] switches = 8'b0;
+ wire [3:0] buttons = 4'b0;
+`else
wire xtalb, clk, vgaclk;
IBUFG iclkbuf(.O(xtalb), .I(xtal));
CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
-
+`endif
+
wire [15:0] addr;
wire [7:0] data;
wire wr, rd;
@@ -224,8 +248,8 @@ module CoreTop(
.vblank(vblankirq),
.lcdc(lcdcirq),
.tovf(tmrirq),
- .serial(0),
- .buttons(0),
+ .serial(1'b0),
+ .buttons(1'b0),
.master(irq),
.jaddr(jaddr));
@@ -239,6 +263,8 @@ module CoreTop(
.snd_data_r(soundr));
endmodule
+`ifdef verilator
+`else
module TestBench();
reg clk = 1;
wire [15:0] addr;
@@ -315,3 +341,4 @@ module TestBench();
.switches(switches),
.ledout(leds));
endmodule
+`endif
diff --git a/Uart.v b/Uart.v
index af173ca..1f0ae7d 100644
--- a/Uart.v
+++ b/Uart.v
@@ -21,14 +21,14 @@ module UART(
reg have_data = 0;
reg [3:0] diqing = 4'b0000;
- wire new = (wr) && (!have_data) && decode;
+ wire newdata = (wr) && (!have_data) && decode;
assign odata = have_data ? 8'b1 : 8'b0;
always @ (negedge clk)
begin
/* deal with diqing */
- if(new) begin
+ if(newdata) begin
data_stor <= data;
have_data <= 1;
diqing <= 4'b0000;
@@ -52,7 +52,7 @@ module UART(
end
/* deal with clkdiv */
- if((new && !have_data) || clkdiv == `CLK_DIV)
+ if((newdata && !have_data) || clkdiv == `CLK_DIV)
clkdiv <= 0;
else
clkdiv <= clkdiv + 1;
diff --git a/mashrom.c b/mashrom.c
index 5c252fe..6ab07a4 100644
--- a/mashrom.c
+++ b/mashrom.c
@@ -1,4 +1,4 @@
-void main(int argc, char** argv)
+int main(int argc, char** argv)
{
int n = 1024;
int i;
@@ -11,4 +11,5 @@ void main(int argc, char** argv)
c = 0;
printf("%02x\n", c);
}
+ return 0;
}
\ No newline at end of file