From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 30 Mar 2008 10:33:25 +0000 (-0400)
Subject: NOP, and bug fixes
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/d3938806a2b49df44ac55ea4b2a43c6a3f15011d?ds=sidebyside

NOP, and bug fixes
---

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 8922cdf..2e6073a 100644
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
diff --git a/GBZ80Core.v b/GBZ80Core.v
index 1aaa01c..3e15ebf 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -33,6 +33,7 @@
 `define INSN_LDH_AC			8'b111x0010	// Either LDH A,(C) or LDH (C),A
 `define INSN_LDx_AHL			8'b001xx010	// LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8				8'b10xxxxxx	// 10 xxx yyy
+`define INSN_NOP				8'b00000000
 
 `define INSN_reg_A		3'b111
 `define INSN_reg_B		3'b000
@@ -333,6 +334,10 @@ module GBZ80Core(
 					endcase
 				end
 			end
+			`INSN_NOP: begin
+				`EXEC_NEWCYCLE;
+				`EXEC_INC_PC;
+			end
 			default:
 				$stop;
 			endcase
@@ -508,7 +513,7 @@ module GBZ80Core(
 							registers[`REG_A] + tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
-							  /* N */ 0,
+							  /* N */ 1'b0,
 							  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
 							  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
 							  registers[`REG_F][3:0]
@@ -519,7 +524,7 @@ module GBZ80Core(
 							registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
-							  /* N */ 0,
+							  /* N */ 1'b0,
 							  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
 							  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
 							  registers[`REG_F][3:0]
@@ -530,7 +535,7 @@ module GBZ80Core(
 							registers[`REG_A] & tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
-							  0,1,0,
+							  3'b010,
 							  registers[`REG_F][3:0]
 							};
 					end
@@ -539,7 +544,7 @@ module GBZ80Core(
 							registers[`REG_A] | tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
-							  0,0,0,
+							  3'b000,
 							  registers[`REG_F][3:0]
 							};
 					end
@@ -548,7 +553,7 @@ module GBZ80Core(
 							registers[`REG_A] ^ tmp;
 						registers[`REG_F] <=
 							{ /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
-							  0,0,0,
+							  3'b000,
 							  registers[`REG_F][3:0]
 							};
 					end
@@ -557,6 +562,7 @@ module GBZ80Core(
 					endcase
 				end
 			end
+			`INSN_NOP: begin /* NOP! */ end
 			endcase
 			state <= `STATE_FETCH;
 		end