From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Fri, 9 May 2008 09:19:01 +0000 (-0400)
Subject: Add an interrupt ack, so that interrupts are cleared automatically. This fixes APOCAL... 
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/d1b404569fd0bdc74a3397c4ef0a5c2e5f95c835

Add an interrupt ack, so that interrupts are cleared automatically. This fixes APOCALYPSE NOW, which we are now running unmodified! Yay!
---

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 3c2f770..29aab52 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -152,7 +152,7 @@ module GBZ80Core(
 	inout [15:0] bus1address,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] bus1data,
 	inout bus1wr, bus1rd,
-	input irq, input [7:0] jaddr,
+	input irq, output reg irqack, input [7:0] jaddr,
 	output reg [1:0] state);
 
 //	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
@@ -282,6 +282,7 @@ module GBZ80Core(
 		cycle <= 0;
 		twobyte <= 0;
 		bootstrap_enb <= 1;
+		irqack <= 0;
 	end
 
 	always @(negedge clk)	/* Set things up at the negedge to prepare for the posedge. */
@@ -341,8 +342,10 @@ module GBZ80Core(
 			state <= `STATE_EXECUTE;
 		end
 		`STATE_EXECUTE: begin
+		`ifdef isim
 			if (opcode[7:0] === 8'bxxxxxxxx)
 				$stop;
+		`endif
 			casex (opcode)
 			`define EXECUTE
 			`include "allinsns.v"
diff --git a/Interrupt.v b/Interrupt.v
index 2686146..201c328 100644
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -13,6 +13,7 @@ module Interrupt(
 	input serial,
 	input buttons,
 	output master,
+	input ack,
 	output [7:0] jaddr);
 
 	wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank};
@@ -45,7 +46,14 @@ module Interrupt(
 			`ADDR_IE : begin imask <= data; ihold <= ihold | iflag; end
 			endcase
 			
-		end
+		end else if (ack)
+			ihold <= ihold &
+				(imasked[0] ? 8'b11111110 :
+				 imasked[1] ? 8'b11111101 :
+				 imasked[2] ? 8'b11111011 :
+				 imasked[3] ? 8'b11110111 :
+				 imasked[4] ? 8'b11101111 :
+				 8'b11111111);
 		else
 			ihold <= ihold | iflag;
 		rdlatch <= rd;
diff --git a/System.v b/System.v
index c2e892b..62f976b 100644
--- a/System.v
+++ b/System.v
@@ -265,6 +265,7 @@ module CoreTop(
 	wire irq, tmrirq, lcdcirq, vblankirq;
 	wire [7:0] jaddr;
 	wire [1:0] state;
+	wire ack;
 	
 	GBZ80Core core(
 		.clk(clk),
@@ -277,6 +278,7 @@ module CoreTop(
 		.bus1wr(wr[1]),
 		.bus1rd(rd[1]),
 		.irq(irq),
+		.irqack(ack),
 		.jaddr(jaddr),
 		.state(state));
 	
@@ -415,6 +417,7 @@ module CoreTop(
 		.serial(1'b0),
 		.buttons(1'b0),
 		.master(irq),
+		.ack(ack),
 		.jaddr(jaddr));
 	
 	Soundcore sound(
diff --git a/insn_vop_intr.v b/insn_vop_intr.v
index 5cb40e1..ce0bcf8 100644
--- a/insn_vop_intr.v
+++ b/insn_vop_intr.v
@@ -3,7 +3,10 @@
 		case (cycle)
 		0:	`EXEC_WRITE(`_SP - 1, `_PCH)
 		1:	`EXEC_WRITE(`_SP - 2, `_PCL)
-		2:	`EXEC_NEWCYCLE
+		2:	begin
+				irqack <= 1;
+				`EXEC_NEWCYCLE
+			end
 		endcase
 	end
 `endif
@@ -16,6 +19,7 @@
 		2:	begin
 				ie <= 0;
 				`_PC <= {8'b0, jaddr};
+				irqack <= 0;	// Must be at the same time as we latch jaddr, or we race!
 				`_SP <= `_SP - 2;
 			end
 		endcase