From: Joshua Wise Date: Wed, 2 Apr 2008 05:21:42 +0000 (-0400) Subject: Working RAM :D X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/c87db60a8f262ec834a46432e5d7b9a4faf09e09?ds=inline Working RAM :D --- diff --git a/FPGABoy.ise b/FPGABoy.ise index d4a916a..f5e4846 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/System.v b/System.v index 033e4b1..dec02b8 100644 --- a/System.v +++ b/System.v @@ -21,19 +21,22 @@ module InternalRAM( input clk, input wr, rd); - reg [7:0] ram [8191:0]; + // synthesis attribute ram_style of reg is block + reg [7:0] ram [2047:0]; - wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00); + wire decode = address[15:13] == 3'b110; reg [7:0] odata; wire idata = data; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; always @(negedge clk) begin - if (decode && rd) - odata <= ram[address[12:0]]; - else if (decode && wr) - ram[address[12:0]] <= data; + if (decode) + begin + if (wr) + ram[address[10:0]] <= data; + odata <= ram[address[10:0]]; + end end endmodule diff --git a/rom.hex b/rom.hex index 6d9f1d9..a37d956 100644 --- a/rom.hex +++ b/rom.hex @@ -8,15 +8,15 @@ df 50 06 00 -cd -23 -00 2a b8 ca 00 00 e2 +cd +23 +00 c3 0a 00