From: Joshua Wise Date: Sat, 19 Apr 2008 10:12:53 +0000 (-0400) Subject: alu_ext X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/c279b66691509cfc4445a568dab29a3282f03f3f?ds=sidebyside alu_ext --- diff --git a/Makefile b/Makefile index 8b2feed..fae41fe 100644 --- a/Makefile +++ b/Makefile @@ -6,7 +6,7 @@ VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \ insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \ insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \ Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v \ - insn_ldbcde_a.v + insn_ldbcde_a.v insn_alu_ext.v insn_bit.v insn_two_byte.v all: CoreTop_rom.svf CoreTop_diag.svf CoreTop_bootrom.svf CoreTop.twr diff --git a/System.v b/System.v index 0e464f5..caa6ae3 100644 --- a/System.v +++ b/System.v @@ -36,6 +36,7 @@ module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */ odata <= ram[address[6:0]]; end end +endmodule module InternalRAM( input [15:0] address, diff --git a/allinsns.v b/allinsns.v index 5ca51d6..6c1c487 100644 --- a/allinsns.v +++ b/allinsns.v @@ -28,3 +28,4 @@ `include "insn_ldbcde_a.v" `include "insn_two_byte.v" `include "insn_bit.v" +`include "insn_alu_ext.v" diff --git a/bootrom.asm b/bootrom.asm index 4f71d5e..b2a2db8 100644 --- a/bootrom.asm +++ b/bootrom.asm @@ -28,8 +28,8 @@ Addr_0007: LD HL,$8010 ; $0024 Addr_0027: LD A,[DE] ; $0027 - CALL $0095 ; $0028 - CALL $0096 ; $002b + CALL a95 ; $0028 + CALL a96 ; $002b INC DE ; $002e LD A,E ; $002f CP $34 ; $0030 @@ -112,8 +112,8 @@ Addr_0086: ; ==== Graphic routine ==== - LD C,A ; $0095 "Double up" all the bits of the graphics data - LD B,$04 ; $0096 and store in Video RAM +a95: LD C,A ; $0095 "Double up" all the bits of the graphics data +a96: LD B,$04 ; $0096 and store in Video RAM Addr_0098: PUSH BC ; $0098 RL C ; $0099 diff --git a/insn_alu_ext.v b/insn_alu_ext.v new file mode 100644 index 0000000..1b7825b --- /dev/null +++ b/insn_alu_ext.v @@ -0,0 +1,45 @@ +`ifdef EXECUTE + `INSN_ALU_EXT: begin + if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) + `EXEC_READ(`_HL) + else begin + `EXEC_INC_PC + case (opcode[2:0]) + `INSN_reg_A: tmp <= `_A; + `INSN_reg_B: tmp <= `_B; + `INSN_reg_C: tmp <= `_C; + `INSN_reg_D: tmp <= `_D; + `INSN_reg_E: tmp <= `_E; + `INSN_reg_H: tmp <= `_H; + `INSN_reg_L: tmp <= `_L; + `INSN_reg_dHL: tmp <= rdata; + endcase + end + end +`endif + +`ifdef WRITEBACK + `INSN_ALU_EXT: begin + if (opcode[2:0] == `INSN_reg_dHL) begin + if(cycle == 0) begin end + else if(cycle == 1) begin + `EXEC_WRITE(`_HL, alu_res) + end else begin + `EXEC_NEWCYCLE + end + end else begin + case(opcode[2:0]) + `INSN_reg_B: `_B <= alu_res; + `INSN_reg_C: `_C <= alu_res; + `INSN_reg_D: `_D <= alu_res; + `INSN_reg_E: `_E <= alu_res; + `INSN_reg_H: `_H <= alu_res; + `INSN_reg_L: `_L <= alu_res; + `INSN_reg_A: `_A <= alu_res; + `INSN_reg_dHL: begin end /* eat dicks */ + endcase + `_F <= {f_res,`_F[3:0]}; + `EXEC_NEWCYCLE + end + end +`endif