From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 4 May 2008 07:56:17 +0000 (-0400)
Subject: Set up the bus a little before the clock.
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/b338a0b6419b53f5c83487d57f5c923d168ae842?hp=58d068d423c00a843a9f1a761503ed685a30a27c

Set up the bus a little before the clock.
---

diff --git a/GBZ80Core.v b/GBZ80Core.v
index ec882da..b06910a 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -280,7 +280,7 @@ module GBZ80Core(
 		bootstrap_enb <= 1;
 	end
 
-	always @(posedge clk)
+	always @(negedge clk)	/* Set things up at the negedge to prepare for the posedge. */
 		case (state)
 		`STATE_FETCH: begin
 			if (newcycle) begin
@@ -294,6 +294,15 @@ module GBZ80Core(
 				if (wr)
 					buswdata <= wdata;
 			end
+		end
+		`STATE_DECODE: begin	/* Make sure this only happens for one clock. */
+		end
+		endcase
+	
+	always @(posedge clk)
+		case (state)
+		`STATE_FETCH: begin
+			/* Things are set up in negedge so that something looking on posedge will get his shit. */
 			state <= `STATE_DECODE;
 		end
 		`STATE_DECODE: begin
@@ -316,10 +325,10 @@ module GBZ80Core(
 				ie <= 1;
 				iedelay <= 0;
 			end
-			buswr <= 0;
-			busrd <= 0;
 			wr <= 0;
 			rd <= 0;
+			buswr <= 0;
+			busrd <= 0;
 			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
 			wdata <= 8'bxxxxxxxx;
 			state <= `STATE_EXECUTE;