From: Joshua Wise Date: Mon, 31 Mar 2008 03:34:09 +0000 (-0400) Subject: Add RET/IRET. Fix a bug in RST where the PC pushed to the stack was incorrect. X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/abae5818eeec14c040361b5181ff1a31cad79868?ds=sidebyside Add RET/IRET. Fix a bug in RST where the PC pushed to the stack was incorrect. --- diff --git a/FPGABoy.ise b/FPGABoy.ise index 8260443..491bbb3 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/GBZ80Core.v b/GBZ80Core.v index 75f9722..c0c2b26 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -35,6 +35,7 @@ `define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy `define INSN_NOP 8'b00000000 `define INSN_RST 8'b11xxx111 +`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 @@ -84,6 +85,8 @@ module GBZ80Core( reg [7:0] buswdata; assign busdata = buswr ? buswdata : 8'bzzzzzzzz; + reg ie = 0; + initial begin registers[ 0] <= 0; registers[ 1] <= 0; @@ -341,17 +344,19 @@ module GBZ80Core( end `INSN_RST: begin case (cycle) - 0: begin + 0: begin + `EXEC_INC_PC; // This goes FIRST + end + 1: begin wr <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; wdata <= registers[`REG_PCH]; end - 1: begin + 2: begin wr <= 1; address <= {registers[`REG_SPH],registers[`REG_SPL]}-2; wdata <= registers[`REG_PCL]; end - 2: begin /* wee */ end 3: begin `EXEC_NEWCYCLE; {registers[`REG_PCH],registers[`REG_PCL]} <= @@ -359,6 +364,23 @@ module GBZ80Core( end endcase end + `INSN_RET: begin + case (cycle) + 0: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}; + end + 1: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1; + end + 2: begin /* twiddle thumbs */ end + 3: begin + `EXEC_NEWCYCLE; + // do NOT increment PC! + end + endcase + end default: $stop; endcase @@ -596,6 +618,26 @@ module GBZ80Core( end endcase end + `INSN_RET: begin + case (cycle) + 0: cycle <= 1; + 1: begin + cycle <= 2; + registers[`REG_PCL] <= rdata; + end + 2: begin + cycle <= 3; + registers[`REG_PCH] <= rdata; + end + 3: begin + cycle <= 0; + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} + 2; + if (opcode[4]) /* RETI */ + ie <= 1; + end + endcase + end endcase state <= `STATE_FETCH; end diff --git a/rom.hex b/rom.hex index b54409e..0cef4b0 100644 --- a/rom.hex +++ b/rom.hex @@ -4,25 +4,13 @@ 01 // LD SP, HL F9 -// POP BC -C1 -// LD A, 10h -3E -10 -// ADD C -81 -// LD H, A -67 -// LD L, 34h -2E -34 -// XOR B -A8 -// LD (HL), A -77 +// RET +C9 + +@80 // RST 00h C7 @100 -02 -44 \ No newline at end of file +80 +00 \ No newline at end of file