From: Joshua Wise Date: Tue, 1 Apr 2008 05:26:45 +0000 (-0400) Subject: JP X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/a85b19a7c7e7fecb4e71c41b37fb30dabaf8bd14?hp=7d9d69c71187b4891b2281ab58ab8360e43290c2 JP --- diff --git a/FPGABoy.ise b/FPGABoy.ise index 5cb2ab7..d10eca1 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/GBZ80Core.v b/GBZ80Core.v index 3bc2b16..1bc8f78 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -37,6 +37,13 @@ `define INSN_RST 8'b11xxx111 `define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET `define INSN_CALL 8'b11001101 +`define INSN_JP_imm 8'b11000011 +`define INSN_JPCC_imm 8'b110xx010 + +`define INSN_cc_NZ 2'b00 +`define INSN_cc_Z 2'b01 +`define INSN_cc_NC 2'b10 +`define INSN_cc_C 2'b11 `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 @@ -423,6 +430,34 @@ module GBZ80Core( end endcase end + `INSN_JP_imm,`INSN_JPCC_imm: begin + case (cycle) + 0: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 1: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 2: begin + if (!opcode[0]) begin // i.e., JP cc,nn + /* We need to check the condition code to bail out. */ + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (!registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (!registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + end + end + 3: begin + `EXEC_NEWCYCLE; + end + endcase + end default: $stop; endcase @@ -656,6 +691,15 @@ module GBZ80Core( end endcase end + `INSN_JP_imm,`INSN_JPCC_imm: begin + case (cycle) + 0: begin /* type F */ end + 1: tmp <= rdata; // tmp contains newpcl + 2: tmp2 <= rdata; // tmp2 contains newpch + 3: {registers[`REG_PCH],registers[`REG_PCL]} <= + {tmp2,tmp}; + endcase + end default: $stop; endcase @@ -663,175 +707,3 @@ module GBZ80Core( end endcase endmodule - -`timescale 1ns / 1ps -module ROM( - input [15:0] address, - inout [7:0] data, - input clk, - input wr, rd); - - reg [7:0] rom [2047:0]; - initial $readmemh("rom.hex", rom); - - wire decode = address[15:13] == 0; - wire [7:0] odata = rom[address[11:0]]; - assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - //assign data = rd ? odata : 8'bzzzzzzzz; -endmodule - -module InternalRAM( - input [15:0] address, - inout [7:0] data, - input clk, - input wr, rd); - - reg [7:0] ram [8191:0]; - - wire decode = (address >= 16'hC000) && (address < 16'hFE00); - reg [7:0] odata; - wire idata = data; - assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - - always @(negedge clk) - begin - if (decode && rd) - odata <= ram[address[12:0]]; - else if (decode && wr) - ram[address[12:0]] <= data; - end -endmodule - -module Switches( - input [15:0] address, - inout [7:0] data, - input clk, - input wr, rd, - input [7:0] switches, - output reg [7:0] ledout); - - wire decode = address == 16'hFF51; - reg [7:0] odata; - wire idata = data; - assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - - always @(negedge clk) - begin - if (decode && rd) - odata <= switches; - else if (decode && wr) - ledout <= data; - end -endmodule - -module CoreTop( - input xtal, - input [1:0] switches, - output wire [7:0] leds, - output serio, - output wire [3:0] digits, - output wire [7:0] seven); - - wire clk; - //IBUFG ibuf (.O(clk), .I(iclk)); - - CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk)); - - wire [15:0] addr; - wire [7:0] data; - wire wr, rd; - - wire [7:0] ledout; - assign leds = switches[1] ? (switches[0]?{rd,wr,addr[5:0]}:data[7:0]) - : ledout; - - GBZ80Core core( - .clk(clk), - .busaddress(addr), - .busdata(data), - .buswr(wr), - .busrd(rd)); - - ROM rom( - .address(addr), - .data(data), - .clk(clk), - .wr(wr), - .rd(rd)); - - AddrMon amon( - .addr(addr), - .clk(clk), - .digit(digits), - .out(seven) - ); - - Switches sw( - .address(addr), - .data(data), - .clk(clk), - .wr(wr), - .rd(rd), - .ledout(ledout), - .switches(0) - ); - - UART nouart ( - .clk(clk), - .wr(wr), - .rd(rd), - .addr(addr), - .data(data), - .serial(serio) - ); -endmodule - -module TestBench(); - reg clk = 0; - wire [15:0] addr; - wire [7:0] data; - wire wr, rd; - -// wire [7:0] leds; -// wire [7:0] switches; - - always #10 clk <= ~clk; - GBZ80Core core( - .clk(clk), - .busaddress(addr), - .busdata(data), - .buswr(wr), - .busrd(rd)); - - ROM rom( - .clk(clk), - .address(addr), - .data(data), - .wr(wr), - .rd(rd)); - -// InternalRAM ram( -// .address(addr), -// .data(data), -// .clk(clk), -// .wr(wr), -// .rd(rd)); - -// wire serio; -// UART uart( -// .addr(addr), -// .data(data), -// .clk(clk), -// .wr(wr), -// .rd(rd), -// .serial(serio)); - -// Switches sw( -// .clk(clk), -// .address(addr), -// .data(data), -// .wr(wr), -// .rd(rd), -// .switches(switches), -// .leds(leds)); -endmodule diff --git a/System.v b/System.v new file mode 100644 index 0000000..53e6257 --- /dev/null +++ b/System.v @@ -0,0 +1,167 @@ + +`timescale 1ns / 1ps +module ROM( + input [15:0] address, + inout [7:0] data, + input clk, + input wr, rd); + + reg [7:0] rom [2047:0]; + initial $readmemh("rom.hex", rom); + + wire decode = address[15:13] == 0; + wire [7:0] odata = rom[address[11:0]]; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; + //assign data = rd ? odata : 8'bzzzzzzzz; +endmodule + +module InternalRAM( + input [15:0] address, + inout [7:0] data, + input clk, + input wr, rd); + + reg [7:0] ram [8191:0]; + + wire decode = (address >= 16'hC000) && (address < 16'hFE00); + reg [7:0] odata; + wire idata = data; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; + + always @(negedge clk) + begin + if (decode && rd) + odata <= ram[address[12:0]]; + else if (decode && wr) + ram[address[12:0]] <= data; + end +endmodule + +module Switches( + input [15:0] address, + inout [7:0] data, + input clk, + input wr, rd, + input [7:0] switches, + output reg [7:0] ledout); + + wire decode = address == 16'hFF51; + reg [7:0] odata; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; + + always @(negedge clk) + begin + if (decode && rd) + odata <= switches; + else if (decode && wr) + ledout <= data; + end +endmodule + +module CoreTop( + input xtal, + input [7:0] switches, + output wire [7:0] leds, + output serio, + output wire [3:0] digits, + output wire [7:0] seven); + + wire clk; + //IBUFG ibuf (.O(clk), .I(iclk)); + + CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk)); + + wire [15:0] addr; + wire [7:0] data; + wire wr, rd; + + GBZ80Core core( + .clk(clk), + .busaddress(addr), + .busdata(data), + .buswr(wr), + .busrd(rd)); + + ROM rom( + .address(addr), + .data(data), + .clk(clk), + .wr(wr), + .rd(rd)); + + AddrMon amon( + .addr(addr), + .clk(clk), + .digit(digits), + .out(seven) + ); + + Switches sw( + .address(addr), + .data(data), + .clk(clk), + .wr(wr), + .rd(rd), + .ledout(leds), + .switches(switches) + ); + + UART nouart ( + .clk(clk), + .wr(wr), + .rd(rd), + .addr(addr), + .data(data), + .serial(serio) + ); +endmodule + +module TestBench(); + reg clk = 0; + wire [15:0] addr; + wire [7:0] data; + wire wr, rd; + +// wire [7:0] leds; +// wire [7:0] switches; + + always #10 clk <= ~clk; + GBZ80Core core( + .clk(clk), + .busaddress(addr), + .busdata(data), + .buswr(wr), + .busrd(rd)); + + ROM rom( + .clk(clk), + .address(addr), + .data(data), + .wr(wr), + .rd(rd)); + +// InternalRAM ram( +// .address(addr), +// .data(data), +// .clk(clk), +// .wr(wr), +// .rd(rd)); + +// wire serio; +// UART uart( +// .addr(addr), +// .data(data), +// .clk(clk), +// .wr(wr), +// .rd(rd), +// .serial(serio)); + +// Switches sw( +// .clk(clk), +// .address(addr), +// .data(data), +// .wr(wr), +// .rd(rd), +// .switches(switches), +// .leds(leds)); +endmodule diff --git a/Uart.v b/Uart.v index f8ee27b..a036c64 100644 --- a/Uart.v +++ b/Uart.v @@ -8,8 +8,13 @@ module UART( input wr, input rd, input [15:0] addr, - input [7:0] data, + inout [7:0] data, output reg serial); + + wire decode = (addr == `MMAP_ADDR); + + wire [7:0] odata; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; reg [7:0] data_stor = 0; reg [15:0] clkdiv = 0; @@ -17,7 +22,9 @@ module UART( reg data_end = 0; reg [3:0] diqing = 4'b0000; - wire new = (wr) && (!have_data) && (addr == `MMAP_ADDR); + wire new = (wr) && (!have_data) && decode; + + assign odata = have_data ? 8'b1 : 8'b0; always @ (negedge clk) begin diff --git a/rom.hex b/rom.hex index 82a8f25..850cf0d 100644 --- a/rom.hex +++ b/rom.hex @@ -2,6 +2,10 @@ 05 DF 0E +51 +F2 +E2 +0E 50 3E 41 @@ -2042,7 +2046,3 @@ C7 00 00 00 -00 -00 -00 -00