From: Joshua Wise <joshua@nyus.joshuawise.com>
Date: Sat, 19 Apr 2008 10:26:26 +0000 (-0400)
Subject: Gate off vraminuse, oaminuse, etc with wehther the LCD is powered on. Make sure to... 
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/a42afaa9d03ed6cd15b1c3d2ec8d4c61c78bf09e

Gate off vraminuse, oaminuse, etc with wehther the LCD is powered on. Make sure to turn the LCD on in the diag rom. Update flags in incdec8.
---

diff --git a/LCDC.v b/LCDC.v
index 5089129..8615443 100644
--- a/LCDC.v
+++ b/LCDC.v
@@ -28,10 +28,9 @@ module LCDC(
 	reg clk4 = 0;
 	always @(posedge clk)
 		clk4 = ~clk4;
-	assign lcdclk = clk4;
 	
 	/***** LCD control registers *****/
-	reg [7:0] rLCDC = 8'h91;
+	reg [7:0] rLCDC = 8'h00;
 	reg [7:0] rSTAT = 8'h00;
 	reg [7:0] rSCY = 8'b00;
 	reg [7:0] rSCX = 8'b00;
@@ -63,8 +62,8 @@ module LCDC(
 	reg [8:0] posx = 9'h000;
 	reg [7:0] posy = 8'h00;
 	
-	wire vraminuse = (posx < 163) && (posy < 144);
-	wire oaminuse = (posx > 369) && (posy < 144);
+	wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
+	wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];
 	
 	wire display = (posx > 2) && (posx < 163) && (posy < 144);
 	
@@ -77,8 +76,9 @@ module LCDC(
 	wire [7:0] vxpos = rSCX + posx - 3;
 	wire [7:0] vypos = rSCY + posy;
 	
-	assign lcdvs = (posy == 153) && (posx == 2);
-	assign lcdhs = (posx == 2);
+	assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
+	assign lcdhs = (posx == 2) && rLCDC[7];
+	assign lcdclk = clk4 && rLCDC[7];
 	
 	wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
 	wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
diff --git a/diag.asm b/diag.asm
index e9fff6a..668452d 100644
--- a/diag.asm
+++ b/diag.asm
@@ -33,6 +33,9 @@ main:
 	ld hl, signon
 	call puts
 
+	ld a, $91
+	ld [$FF40], a
+
 	call putscreen
 	
 	ei
diff --git a/insn_incdec_reg8.v b/insn_incdec_reg8.v
index 78f8b5a..61464f6 100644
--- a/insn_incdec_reg8.v
+++ b/insn_incdec_reg8.v
@@ -25,5 +25,10 @@
 		`INSN_reg_H:	`_H <= tmp + (opcode[0] ? 8'hFF : 8'h01);
 		`INSN_reg_L:	`_L <= tmp + (opcode[0] ? 8'hFF : 8'h01);
 		endcase
+		`_F <= {
+				(tmp + (opcode[0] ? 8'hFF : 8'h01)) ? 1'b0 : 1'b1,
+				1'b0,
+				(({1'b0,tmp[3:0]} + (opcode[0] ? 5'h1F : 5'h01)) >> 4) ? 1'b1 : 1'b0,
+				`_F[4:0]};
 	end
 `endif