From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Tue, 1 Apr 2008 08:11:17 +0000 (-0400)
Subject: Test RAM
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/9aa931d18d08b0542f8fae054fba96a9e7b095ea?ds=sidebyside;hp=6493be2b598bd598f939245dbd8a9ae4b242f407

Test RAM
---

diff --git a/FPGABoy.ise b/FPGABoy.ise
index c429431..aeefb4a 100644
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
diff --git a/System.v b/System.v
index 259656a..8fc4c9c 100644
--- a/System.v
+++ b/System.v
@@ -23,7 +23,7 @@ module InternalRAM(
 	
 	reg [7:0] ram [8191:0];
 	
-	wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+	wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
 	reg [7:0] odata;
 	wire idata = data;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
@@ -114,6 +114,13 @@ module CoreTop(
     .data(data), 
     .serial(serio)
     );
+
+  InternalRAM ram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd));
 endmodule
 
 module TestBench();
@@ -140,12 +147,12 @@ module TestBench();
 		.wr(wr),
 		.rd(rd));
 	
-//	InternalRAM ram(
-//		.address(addr),
-//		.data(data),
-//		.clk(clk),
-//		.wr(wr),
-//		.rd(rd));
+	InternalRAM ram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd));
 
 	wire serio;
 	UART uart(
diff --git a/rom.hex b/rom.hex
index 504108d..8ccdb42 100644
--- a/rom.hex
+++ b/rom.hex
@@ -1,19 +1,18 @@
+31
+ff
+df
 0e
 50
 06
 00
-f2
-b8
-c2
-04
+cd
+16
 00
 3e
 41
 e2
-f2
-b8
-c2
-0c
+cd
+16
 00
 3e
 42
@@ -21,11 +20,12 @@ e2
 c3
 00
 00
+f2
+b8
+c2
+16
 00
-00
-00
-00
-00
+c9
 00
 00
 00