From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 4 May 2008 08:02:22 +0000 (-0400)
Subject: Flop the clock polarity of the LCDC around.
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/8e2bb38447e731bbba10c39cfb995b9b4eccd22c?hp=68ce013e5fe7c5d1c4e07fe8ba1eb0ba2855b280

Flop the clock polarity of the LCDC around.
---

diff --git a/LCDC.v b/LCDC.v
index 7b402e4..f951d3a 100644
--- a/LCDC.v
+++ b/LCDC.v
@@ -88,7 +88,7 @@ module LCDC(
 	assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
 	assign vblankirq = (posx == 0 && posy == 153);
 	
-	always @(posedge clk4)
+	always @(negedge clk4)
 	begin
 		if (posx == 455) begin
 			posx <= 0;
@@ -154,14 +154,14 @@ module LCDC(
 	wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
 	wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
 	
-	always @(negedge clk)
+	always @(posedge clk)
 		if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
 			tileno <= bgmap1[bgmapaddr_in];
 			if (wr && decode_bgmap1 && ~vraminuse)
 				bgmap1[bgmapaddr_in] <= data;
 		end
 	
-	always @(negedge clk)
+	always @(posedge clk)
 		if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
 			tilehigh <= tiledatahigh[tileaddr_in];
 			tilelow <= tiledatalow[tileaddr_in];
@@ -190,7 +190,7 @@ module LCDC(
 			 8'bzzzzzzzz) :
 		8'bzzzzzzzz;
   
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (wr)
 			case (addr)