From: Joshua Wise Date: Tue, 1 Apr 2008 03:58:32 +0000 (-0400) Subject: Spit lots of A out of the UART. X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/7d9d69c71187b4891b2281ab58ab8360e43290c2 Spit lots of A out of the UART. --- diff --git a/CPUDCM.xaw b/CPUDCM.xaw index f28ae93..28c7791 100644 --- a/CPUDCM.xaw +++ b/CPUDCM.xaw @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.4e 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fc77377..3bc2b16 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -702,30 +702,31 @@ module InternalRAM( end endmodule -//module Switches( -// input [15:0] address, -// inout [7:0] data, -// input clk, -// input wr, rd, -// input [7:0] switches, -// output reg [7:0] ledout); +module Switches( + input [15:0] address, + inout [7:0] data, + input clk, + input wr, rd, + input [7:0] switches, + output reg [7:0] ledout); -// wire decode = address == 16'hFF51; -// reg [7:0] odata; -// wire idata = data; -// assign data = (rd && decode) ? odata : 8'bzzzzzzzz; + wire decode = address == 16'hFF51; + reg [7:0] odata; + wire idata = data; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; -// always @(negedge clk) -// begin -// if (decode && rd) -// odata <= switches; -// else if (decode && wr) -// ledout <= data; -// end -//endmodule + always @(negedge clk) + begin + if (decode && rd) + odata <= switches; + else if (decode && wr) + ledout <= data; + end +endmodule module CoreTop( - input iclk, xtal, + input xtal, + input [1:0] switches, output wire [7:0] leds, output serio, output wire [3:0] digits, @@ -740,7 +741,9 @@ module CoreTop( wire [7:0] data; wire wr, rd; - assign leds = iclk?{rd,wr,addr[5:0]}:data[7:0]; + wire [7:0] ledout; + assign leds = switches[1] ? (switches[0]?{rd,wr,addr[5:0]}:data[7:0]) + : ledout; GBZ80Core core( .clk(clk), @@ -758,12 +761,29 @@ module CoreTop( AddrMon amon( .addr(addr), - .clk(xtal), + .clk(clk), .digit(digits), .out(seven) ); - - assign serio = 0; + + Switches sw( + .address(addr), + .data(data), + .clk(clk), + .wr(wr), + .rd(rd), + .ledout(ledout), + .switches(0) + ); + + UART nouart ( + .clk(clk), + .wr(wr), + .rd(rd), + .addr(addr), + .data(data), + .serial(serio) + ); endmodule module TestBench(); diff --git a/Uart.v b/Uart.v index 1cc839a..f8ee27b 100644 --- a/Uart.v +++ b/Uart.v @@ -1,4 +1,4 @@ -`define IN_CLK 8400000 +`define IN_CLK 8388608 `define OUT_CLK 9600 `define CLK_DIV `IN_CLK / `OUT_CLK `define MMAP_ADDR 16'hFF50 @@ -21,17 +21,16 @@ module UART( always @ (negedge clk) begin -`define FUQING 4'b1010 /* deal with diqing */ if(new) begin - data_stor <= ~data; + data_stor <= data; have_data <= 1; diqing <= 4'b0000; end else if (clkdiv == 0) begin diqing <= diqing + 1; if (have_data) case (diqing) - 4'b0000: serial <= 1; + 4'b0000: serial <= 0; 4'b0001: serial <= data_stor[0]; 4'b0010: serial <= data_stor[1]; 4'b0011: serial <= data_stor[2]; @@ -40,7 +39,7 @@ module UART( 4'b0110: serial <= data_stor[5]; 4'b0111: serial <= data_stor[6]; 4'b1000: serial <= data_stor[7]; - 4'b1001: serial <= 0; + 4'b1001: serial <= 1; 4'b1010: have_data <= 0; default: $stop; endcase diff --git a/rom.hex b/rom.hex index 79290c3..82a8f25 100644 --- a/rom.hex +++ b/rom.hex @@ -2,9 +2,9 @@ 05 DF 0E -51 +50 3E -40 +41 E2 C7 00