From: Joshua Wise Date: Tue, 6 May 2008 11:48:49 +0000 (-0400) Subject: Fix some really dumb no-synthesize issues LIKE NOT TYPING THE MODULE NAME CORRECTLY... X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/7c1b9e8ea3a9ec0d0c00009df9212a1829e072ec?ds=inline Fix some really dumb no-synthesize issues LIKE NOT TYPING THE MODULE NAME CORRECTLY c.c;;;;;;;;;;;;;;;;;; --- diff --git a/GBZ80Core.v b/GBZ80Core.v index 8970e5d..e1aa308 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -333,8 +333,6 @@ module GBZ80Core( end wr <= 0; rd <= 0; - buswr <= 0; - busrd <= 0; address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened. wdata <= 8'bxxxxxxxx; state <= `STATE_EXECUTE; diff --git a/System.v b/System.v index 95b715c..b1d4c3d 100644 --- a/System.v +++ b/System.v @@ -262,11 +262,11 @@ module CoreTop( .data(data[0]), .clk(clk), .wr(wr[0]), - .rd(rd[0]) + .rd(rd[0]), .cr_nADV(cr_nADV), .cr_nCE(cr_nCE), .cr_nOE(cr_nOE), - .cr_nWR(cr_nWE), + .cr_nWE(cr_nWE), .cr_CRE(cr_CRE), .cr_nLB(cr_nLB), .cr_nUB(cr_nUB),