From: Joshua Wise Date: Tue, 6 May 2008 09:01:40 +0000 (-0400) Subject: Add cut 1 of a cellram module X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/74610a872e3bead82589e6ea786e928f319540e4?ds=sidebyside Add cut 1 of a cellram module --- diff --git a/System.v b/System.v index 1872e51..4d0ddbb 100644 --- a/System.v +++ b/System.v @@ -55,6 +55,57 @@ module MiniRAM( end endmodule +module CellularRAM( + input clk, + input [15:0] address, + inout [7:0] data, + input wr, rd, + output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, + output wire [22:0] cr_A, + inout [15:0] cr_DQ); + + parameter ADDR_PROGADDRH = 16'hFF60; + parameter ADDR_PROGADDRM = 16'hFF61; + parameter ADDR_PROGADDRL = 16'hFF62; + parameter ADDR_PROGDATA = 16'hFF63; + + reg [7:0] progaddrh, progaddrm, progaddrl; + + assign cr_nADV = 0; /* Addresses are always valid! :D */ + assign cr_nCE = 0; /* The chip is enabled */ + assign cr_nLB = 0; /* Lower byte is enabled */ + assign cr_nUB = 0; /* Upper byte is enabled */ + assign cr_CRE = 0; /* Data writes, not config */ + assign cr_CLK = 0; /* Clock? I think not! */ + + wire decode = (address[15:14] == 2'b00) /* extrom */ || (address[15:13] == 3'b101) /* extram */ || (address == ADDR_PROGDATA); + + assign cr_nOE = decode ? ~rd : 1; + assign cr_nWE = decode ? ~wr : 1; + + assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, data}; + assign cr_A = (address[15:14] == 2'b00) ? /* extrom */ {9'b0,address[13:0]} : + (address[15:13] == 3'b101) ? {1'b1, 9'b0, address[12:0]} : + (address == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} : + 23'b0; + + reg [7:0] regbuf; + + always @(posedge clk) + case (address) + ADDR_PROGADDRH: if (wr) progaddrh <= data; + ADDR_PROGADDRM: if (wr) progaddrm <= data; + ADDR_PROGADDRL: if (wr) progaddrl <= data; + endcase + + assign data = (rd && decode) ? + (address == ADDR_PROGADDRH) ? progaddrh : + (address == ADDR_PROGADDRM) ? progaddrm : + (address == ADDR_PROGADDRL) ? progaddrl : + cr_DQ + : 8'bzzzzzzzz; +endmodule + module InternalRAM( input [15:0] address, inout [7:0] data, @@ -64,14 +115,14 @@ module InternalRAM( // synthesis attribute ram_style of ram is block reg [7:0] ram [8191:0]; - wire decode = address[15:13] == 3'b110; + wire decode = (address >= 16'hC000) && (address <= 16'hFDFF); /* This includes echo RAM. */ reg [7:0] odata; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; always @(posedge clk) begin - if (decode) // This has to go this way. The only way XST knows how to do - begin // block ram is chip select, write enable, and always + if (decode) // This has to go this way. The only way XST knows how to do + begin // block ram is chip select, write enable, and always if (wr) // reading. "else if rd" does not cut it ... ram[address[12:0]] <= data; odata <= ram[address[12:0]]; @@ -117,6 +168,9 @@ module CoreTop( output serio, output wire [3:0] digits, output wire [7:0] seven, + output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, + output wire [22:0] cr_A, + inout [15:0] cr_DQ, `endif output wire hs, vs, output wire [2:0] r, g, @@ -171,12 +225,31 @@ module CoreTop( .wr(wr[1]), .rd(rd[1])); +`ifdef isim ROM rom( .address(addr[0]), .data(data[0]), .clk(clk), .wr(wr[0]), .rd(rd[0])); +`else + CellularRAM cellram( + .address(addr[0]), + .data(data[0]), + .clk(clk), + .wr(wr[0]), + .rd(rd[0]) + .cr_nADV(cr_nADV), + .cr_nCE(cr_nCE), + .cr_nOE(cr_nOE), + .cr_nWR(cr_nWE), + .cr_CRE(cr_CRE), + .cr_nLB(cr_nLB), + .cr_nUB(cr_nUB), + .cr_CLK(cr_CLK), + .cr_A(cr_A), + .cr_DQ(cr_DQ)); +`endif wire lcdhs, lcdvs, lcdclk; wire [2:0] lcdr, lcdg;