From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 30 Mar 2008 10:04:28 +0000 (-0400)
Subject: ADC, AND, OR, XOR
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/6dbce0b54fbfff7fee918b9033c0111065ce582a?ds=inline;hp=94522011a1aecc56d0718817bd4ffeb6b650b308

ADC, AND, OR, XOR
---

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 0cdefa5..1aaa01c 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -514,6 +514,44 @@ module GBZ80Core(
 							  registers[`REG_F][3:0]
 							};
 					end
+					`INSN_alu_ADC: begin
+						registers[`REG_A] <=
+							registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
+						registers[`REG_F] <=
+							{ /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
+							  /* N */ 0,
+							  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
+							  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
+							  registers[`REG_F][3:0]
+							};
+					end
+					`INSN_alu_AND: begin
+						registers[`REG_A] <=
+							registers[`REG_A] & tmp;
+						registers[`REG_F] <=
+							{ /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
+							  0,1,0,
+							  registers[`REG_F][3:0]
+							};
+					end
+					`INSN_alu_OR: begin
+						registers[`REG_A] <=
+							registers[`REG_A] | tmp;
+						registers[`REG_F] <=
+							{ /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
+							  0,0,0,
+							  registers[`REG_F][3:0]
+							};
+					end
+					`INSN_alu_XOR: begin
+						registers[`REG_A] <=
+							registers[`REG_A] ^ tmp;
+						registers[`REG_F] <=
+							{ /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
+							  0,0,0,
+							  registers[`REG_F][3:0]
+							};
+					end
 					default:
 						$stop;
 					endcase