From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Fri, 4 Apr 2008 03:09:44 +0000 (-0400)
Subject: Add JP HL, add CALL CC
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/6b4e28281b4fa98272bead1eedeea577e8778169

Add JP HL, add CALL CC
---

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 7374a59..d8f72a2 100644
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
diff --git a/GBZ80Core.v b/GBZ80Core.v
index e125225..0697295 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -37,9 +37,11 @@
 `define INSN_RST				8'b11xxx111
 `define INSN_RET				8'b110x1001	// 1 = RETI, 0 = RET
 `define INSN_CALL				8'b11001101
+`define INSN_CALLCC			8'b110xx100	// Not that call/cc.
 `define INSN_JP_imm			8'b11000011
 `define INSN_JPCC_imm		8'b110xx010
 `define INSN_ALU_A		8'b00xxx111
+`define INSN_JP_HL			8'b11101001
 
 `define INSN_cc_NZ			2'b00
 `define INSN_cc_Z				2'b01
@@ -413,7 +415,7 @@ module GBZ80Core(
 					end
 				endcase
 			end
-			`INSN_CALL: begin
+			`INSN_CALL,`INSN_CALLCC: begin
 				case (cycle)
 				0:	begin
 						`EXEC_INC_PC;
@@ -427,6 +429,14 @@ module GBZ80Core(
 					end
 				2:	begin
 						`EXEC_INC_PC;
+						if (!opcode[0])	// i.e., is callcc
+							/* We need to check the condition code to bail out. */
+							case (opcode[4:3])
+							`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+							endcase
 					end
 				3:	begin
 						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
@@ -472,6 +482,9 @@ module GBZ80Core(
 					end
 				endcase
 			end
+			`INSN_JP_HL: begin
+				`EXEC_NEWCYCLE;
+			end
 			default:
 				$stop;
 			endcase
@@ -752,7 +765,7 @@ module GBZ80Core(
 					end
 				endcase
 			end
-			`INSN_CALL: begin
+			`INSN_CALL,`INSN_CALLCC: begin
 				case (cycle)
 				0:	begin /* type F */ end
 				1:	tmp <= rdata;	// tmp contains newpcl
@@ -775,6 +788,10 @@ module GBZ80Core(
 						{tmp2,tmp};
 				endcase
 			end
+			`INSN_JP_HL: begin
+				{registers[`REG_PCH],registers[`REG_PCL]} <=
+					{registers[`REG_H],registers[`REG_L]};
+			end
 			default:
 				$stop;
 			endcase