From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Fri, 4 Apr 2008 08:23:12 +0000 (-0400)
Subject: Timer works.
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/62940da0dd1b60db11e9861d6dd55a43c5756114?hp=06ad3a30038ac8ca45dd7b0c34213c0c8335c17c

Timer works.
---

diff --git a/FPGABoy.ise b/FPGABoy.ise
index a4399b8..2278455 100644
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
diff --git a/GBZ80Core.v b/GBZ80Core.v
index 96e4dcd..095d9e8 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -87,9 +87,9 @@
 
 module GBZ80Core(
 	input clk,
-	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
+	output reg [15:0] busaddress = 0,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
-	output reg buswr, output reg busrd);
+	output reg buswr = 0, output reg busrd = 0);
 	
 	reg [1:0] state = 0;					/* State within this bus cycle (see STATE_*). */
 	reg [2:0] cycle = 0;					/* Cycle for instructions. */
diff --git a/Interrupt.v b/Interrupt.v
index 4e3d17d..1450b2c 100644
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -17,7 +17,7 @@ module Interrupt(
 
 	wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank};
 	reg [7:0] imask = 16'hFFFF;
-	reg [7:0] ihold = 0;
+	reg [7:0] ihold = 8'b0;
 	wire [7:0] imasked = ihold & imask;
 
 	assign data = rd ?
@@ -34,12 +34,12 @@ module Interrupt(
 		       imasked[3] ? 8'h58 :
 		       imasked[4] ? 8'h60 : 8'h00;
 
-	always @ (negedge clk)
+	always @(negedge clk)
 	begin
-		if (wr) begin
+		if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
 			case(addr)
 			`ADDR_IF : ihold <= iflag | data;
-			`ADDR_IE : imask <= data;
+			`ADDR_IE : begin imask <= data; ihold <= ihold | iflag; end
 			endcase
 			
 		end
diff --git a/System.v b/System.v
index a5fee66..8b8d613 100644
--- a/System.v
+++ b/System.v
@@ -151,7 +151,7 @@ module CoreTop(
 endmodule
 
 module TestBench();
-	reg clk = 0;
+	reg clk = 1;
 	wire [15:0] addr;
 	wire [7:0] data;
 	wire wr, rd;
diff --git a/Timer.v b/Timer.v
index 0481614..53f392d 100644
--- a/Timer.v
+++ b/Timer.v
@@ -9,11 +9,11 @@ module Timer(
 	input rd,
 	input [15:0] addr,
 	inout [7:0] data,
-	output reg irq);
+	output reg irq = 0);
 
 	reg [7:0] tima = 0, tma = 0, tac = 0, div = 0;
 	reg ovf = 0;
-	reg [9:0] clkdv;
+	reg [9:0] clkdv = 0;
 
 	wire is_tima = addr == `ADDR_TIMA;
 	wire is_tma  = addr == `ADDR_TMA;
diff --git a/rom.asm b/rom.asm
index 93f8524..5527ea8 100644
--- a/rom.asm
+++ b/rom.asm
@@ -4,7 +4,7 @@ main:
 	ld c, $51	; Note that we are alive.
 	ld a, $FF
 	ld [c],a
-
+	
 	ld sp, $DFFF
 
 	ld hl, signon
@@ -105,7 +105,7 @@ waitsw:
 	call puts
 	
 	ld c, $07
-	ld a, $07	;start timer, 4.096KHz
+	ld a, $04	;start timer, 4.096KHz
 	ld [c], a
 	
 	ld c, $51
@@ -138,13 +138,8 @@ testa:
 	ret z
 	xor a
 	ld [c], a
-	ld hl, $D000
-	ld c, [hl]
-	inc bc
-	ld [hl], c
-	ld a, c
-	ld c, $50
-	ld [c], a
+	ld a, $41
+	call putc
 	ret
 
 ; Core instruction basic acceptance tests.
@@ -258,10 +253,12 @@ insntest:
 putc:
 	ld b, 0
 	ld c, $50
+	push af
 .waitport:
 	ld a,[c]
 	cp b
 	jr nz,.waitport
+	pop af
 	ld [c],a
 	ret
 
@@ -269,6 +266,8 @@ puts:
 	ld a, [hli]
 	ld b, $00
 	cp b
-	ret z
+	jr z, .done
 	call putc
 	jr puts
+.done:
+	ret