From: Joshua Wise Date: Mon, 31 Mar 2008 06:58:27 +0000 (-0400) Subject: Fix RAM bugs with kludge. Fix CALL bug. CALL test case. X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/4f9c2edfd1242be9e98667d39393c829fcd826c8?hp=ef6fbe3130c958177759bd99cf24a6c3edc4693c Fix RAM bugs with kludge. Fix CALL bug. CALL test case. --- diff --git a/FPGABoy.ise b/FPGABoy.ise index 5ae1765..8ee44c4 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/GBZ80Core.v b/GBZ80Core.v index cb231c2..ec1756e 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -395,16 +395,18 @@ module GBZ80Core( rd <= 1; end 2: begin + `EXEC_INC_PC; + end + 3: begin address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1; wdata <= registers[`REG_PCH]; wr <= 1; end - 3: begin + 4: begin address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; wdata <= registers[`REG_PCL]; wr <= 1; end - 4: begin /* nothing happens on the bus next cycle! */ end 5: begin `EXEC_NEWCYCLE; /* do NOT increment the PC */ end @@ -680,15 +682,15 @@ module GBZ80Core( end 3: begin cycle <= 4; - registers[`REG_PCH] <= tmp2; end 4: begin cycle <= 5; - registers[`REG_PCL] <= tmp; + registers[`REG_PCH] <= tmp2; end 5: begin {registers[`REG_SPH],registers[`REG_SPL]} <= {registers[`REG_SPH],registers[`REG_SPL]} - 2; + registers[`REG_PCL] <= tmp; cycle <= 0; end endcase @@ -715,16 +717,15 @@ module ROM( wire idata = data; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - always @(wr or rd) - begin - if (decode && rd) + always @(posedge rd) + if (decode) odata <= rom[address]; - end endmodule module InternalRAM( input [15:0] address, inout [7:0] data, + input clk, input wr, rd); reg [7:0] ram [8191:0]; @@ -734,12 +735,17 @@ module InternalRAM( wire idata = data; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - always @(rd or wr) + reg [13:0] diq; + initial + for (diq = 0; diq < 8191; diq = diq + 1) + ram[diq] = 8'h43; + + always @(negedge clk) begin if (decode && rd) - odata <= ram[address]; - else if (decode && wr) - ram[address] <= idata; + odata <= ram[address[12:0]]; + if (decode && wr) + ram[address[12:0]] <= data; end endmodule @@ -766,6 +772,7 @@ module TestBench(); InternalRAM ram( .address(addr), .data(data), + .clk(clk), .wr(wr), .rd(rd)); endmodule diff --git a/rom.hex b/rom.hex index 0cef4b0..5ff2d7a 100644 --- a/rom.hex +++ b/rom.hex @@ -1,16 +1,18 @@ -// LD HL, 0100 -21 -00 +// LD SP, DFFFh +31 +FF +DF +// CALL 0080h +CD +80 +01 +// CALL 0080h +CD +80 01 -// LD SP, HL -F9 -// RET -C9 - -@80 // RST 00h C7 -@100 -80 -00 \ No newline at end of file +@180 +// RET +C9