From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 2 Apr 2008 03:25:12 +0000 (-0400)
Subject: Fix bug in UART where idle state is not entered by default
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/1e26cecc7eb53d2765d7a4d7f21ceca81e165409?ds=sidebyside;hp=220259df1528654383aa63bb1a41f7a87181f599

Fix bug in UART where idle state is not entered by default
---

diff --git a/Uart.v b/Uart.v
index a036c64..f87005d 100644
--- a/Uart.v
+++ b/Uart.v
@@ -9,7 +9,7 @@ module UART(
 	input rd,
 	input [15:0] addr,
 	inout [7:0] data,
-	output reg serial);
+	output reg serial = 1);
 	
 	wire decode = (addr == `MMAP_ADDR);