From: Joshua Wise Date: Sun, 30 Mar 2008 07:06:08 +0000 (-0400) Subject: LDH A,(C) and LDH (C), A X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/00e30b4dd08f216cc9fe89295f575b9b7d0622b5?ds=sidebyside LDH A,(C) and LDH (C), A --- diff --git a/FPGABoy.ise b/FPGABoy.ise index fe38e42..d632f1e 100644 Binary files a/FPGABoy.ise and b/FPGABoy.ise differ diff --git a/GBZ80Core.v b/GBZ80Core.v index 968cd26..1d06b12 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -29,7 +29,8 @@ `define INSN_LD_reg_imm16 8'b00xx0001 `define INSN_LD_SP_HL 8'b11111001 `define INSN_PUSH_reg 8'b11xx0101 -`define INSN_POP_reg 8'b11xx0001 +`define INSN_POP_reg 8'b11xx0001 +`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 `define INSN_reg_C 3'b001 @@ -266,6 +267,23 @@ module GBZ80Core( end endcase end + `INSN_LDH_AC: begin + case (cycle) + 0: begin + address <= {8'hFF,registers[`REG_C]}; + if (opcode[4]) begin // LD A,(C) + rd <= 1; + end else begin + wr <= 1; + wdata <= {8'hFF,registers[`REG_A]}; + end + end + 1: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end + endcase + end default: $stop; endcase @@ -405,7 +423,17 @@ module GBZ80Core( cycle <= 0; end endcase - end + end + `INSN_LDH_AC: begin + case (cycle) + 0: cycle <= 1; + 1: begin + cycle <= 0; + if (opcode[4]) + registers[`REG_A] <= rdata; + end + endcase + end endcase state <= `STATE_FETCH; end diff --git a/rom.hex b/rom.hex index 00214cd..c86844c 100644 --- a/rom.hex +++ b/rom.hex @@ -20,5 +20,5 @@ C1 76 @100 -00 +50 56