Yay. Fix retcc. Comparing against an x value - great idea, or greatest idea?

diff --git a/FPGABoy.ise b/FPGABoy.ise
index b09f3837ef1027e88526812c8eda91499b2c5638..1d807e94bddb9631ff953512bd9ebefdfa15a801 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index cd7f4d1cb35861e609888a53b3f1dc70368edbd2..3cd46e3b1cec513536674259e0045391975673d7 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -401,7 +401,7 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

-                       `INSN_RET: begin
+                       `INSN_RET,`INSN_RETCC: begin

                                case (cycle)
                                0:      begin
                                                rd <= 1;
                                case (cycle)
                                0:      begin
                                                rd <= 1;


@@ -409,8 +409,6 @@ module GBZ80Core(
                                        end
                                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
                                                `EXEC_INC_PC;
                                        end
                                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
                                                `EXEC_INC_PC;

-                                               if (opcode != `INSN_RETCC)
-                                                       $stop;

                                                case (opcode[4:3])      // cycle 1 is skipped if we are not retcc
                                                `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
                                                `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
                                                case (opcode[4:3])      // cycle 1 is skipped if we are not retcc
                                                `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
                                                `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end


@@ -794,7 +792,7 @@ module GBZ80Core(
                        end
                        `INSN_RET,`INSN_RETCC: begin
                                case (cycle)
                        end
                        `INSN_RET,`INSN_RETCC: begin
                                case (cycle)

-                               0:      if (opcode != `INSN_RETCC)
+                               0:      if (opcode[0])  // i.e., not RETCC

                                                cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
                                1: begin /* Nothing need happen here. */ end
                                2:      registers[`REG_PCL] <= rdata;
                                                cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
                                1: begin /* Nothing need happen here. */ end
                                2:      registers[`REG_PCL] <= rdata;

diff --git a/rom.asm b/rom.asm
index aa070ff2c0f33633af42231b746e09b771c53e0a..d650855e429cdb8c222197d8c401cf8c6bb985f8 100644 (file)
--- a/rom.asm
+++ b/rom.asm
@@ -212,7 +212,7 @@ insntest:
 .cplfail:
        db "CPL",0
 .testfailed:
 .cplfail:
        db "CPL",0
 .testfailed:

-       db "test failed.",$0D,$0A,0
+       db " test failed.",$0D,$0A,0

 .ok:
        db "OK!",$0D,$0A,0
 
 .ok:
        db "OK!",$0D,$0A,0
 


@@ -233,9 +233,6 @@ puts:
        ld a, [hli]
        ld b, $00
        cp b
        ld a, [hli]
        ld b, $00
        cp b

-       jr z, .done
+       ret z

        call putc
        jr puts
        call putc
        jr puts

-.done:
-       ret
-