Add inc16 test, and inc16 and dec16.

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 1d807e94bddb9631ff953512bd9ebefdfa15a801..b37a4cd4a6aa14bcf61f188bfef1232cbfa5819a 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 3cd46e3b1cec513536674259e0045391975673d7..96e4dcd38a164996df038dca0232ab82a837e90e 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -45,6 +45,7 @@
 `define INSN_JP_HL                     8'b11101001
 `define INSN_JR_imm                    8'b00011000
 `define INSN_JRCC_imm          8'b001xx000
+`define INSN_INCDEC16          8'b00xxx011
 
 `define INSN_cc_NZ                     2'b00
 `define INSN_cc_Z                              2'b01
@@ -408,8 +409,8 @@ module GBZ80Core(
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end
                                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
-                                               `EXEC_INC_PC;
-                                               case (opcode[4:3])      // cycle 1 is skipped if we are not retcc
+                                               `EXEC_INC_PC;   // cycle 1 is skipped if we are not retcc
+                                               case (opcode[4:3])
                                                `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
                                                `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
                                                `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
@@ -523,6 +524,34 @@ module GBZ80Core(
                                        end
                                endcase
                        end
+                       `INSN_INCDEC16: begin
+                               case (cycle)
+                               0: begin
+                                               case (opcode[5:4])
+                                               `INSN_reg16_BC: begin
+                                                       tmp <= registers[`REG_B];
+                                                       tmp2 <= registers[`REG_C];
+                                               end
+                                               `INSN_reg16_DE: begin
+                                                       tmp <= registers[`REG_D];
+                                                       tmp2 <= registers[`REG_E];
+                                               end
+                                               `INSN_reg16_HL: begin
+                                                       tmp <= registers[`REG_H];
+                                                       tmp2 <= registers[`REG_L];
+                                               end
+                                               `INSN_reg16_SP: begin
+                                                       tmp <= registers[`REG_SPH];
+                                                       tmp2 <= registers[`REG_SPL];
+                                               end
+                                               endcase
+                                       end
+                               1: begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
+                       end
                        default:
                                $stop;
                        endcase
@@ -800,7 +829,7 @@ module GBZ80Core(
                                4:      begin
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 2;
-                                               if (opcode[4] && (opcode != `INSN_RETCC))       /* RETI */
+                                               if (opcode[4] && opcode[0])     /* RETI */
                                                        ie <= 1;
                                        end
                                endcase
@@ -841,6 +870,32 @@ module GBZ80Core(
                                                {tmp[7]?8'hFF:8'h00,tmp};
                                endcase
                        end
+                       `INSN_INCDEC16: begin
+                               case (cycle)
+                               0:      {tmp,tmp2} <= {tmp,tmp2} +
+                                               (opcode[3] ? 16'hFFFF : 16'h0001);
+                               1: begin
+                                               case (opcode[5:4])
+                                               `INSN_reg16_BC: begin
+                                                       registers[`REG_B] <= tmp;
+                                                       registers[`REG_C] <= tmp2;
+                                               end
+                                               `INSN_reg16_DE: begin
+                                                       registers[`REG_D] <= tmp;
+                                                       registers[`REG_E] <= tmp2;
+                                               end
+                                               `INSN_reg16_HL: begin
+                                                       registers[`REG_H] <= tmp;
+                                                       registers[`REG_L] <= tmp2;
+                                               end
+                                               `INSN_reg16_SP: begin
+                                                       registers[`REG_SPH] <= tmp;
+                                                       registers[`REG_SPL] <= tmp2;
+                                               end
+                                               endcase
+                                       end
+                               endcase
+                       end
                        default:
                                $stop;
                        endcase

diff --git a/rom.asm b/rom.asm
index d650855e429cdb8c222197d8c401cf8c6bb985f8..2e98e136fb592519941823a6fa3a865d96b54f0d 100644 (file)
--- a/rom.asm
+++ b/rom.asm
@@ -167,6 +167,18 @@ insntest:
        jr .fail
        rst $00
 .jr:
+
+       ; Test inc16
+       ld d, $12
+       ld e, $FF
+       ld hl, .inc16fail
+       inc de
+       ld a, $13
+       cp d
+       jr nz, .fail
+       ld a, $00
+       cp e
+       jr nz, .fail
        
        ; Test CP.
        ld hl, .cpfail
@@ -211,6 +223,8 @@ insntest:
        db "CP",0
 .cplfail:
        db "CPL",0
+.inc16fail:
+       db "INC16",0
 .testfailed:
        db " test failed.",$0D,$0A,0
 .ok: