Working RAM :D

diff --git a/FPGABoy.ise b/FPGABoy.ise
index d4a916a5f7759f4d14c255ffddca171e7c98d73e..f5e4846968d62f15f873fc0119d7e4ab80c6f52c 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/System.v b/System.v
index 033e4b180bca090e52953022b3b5f94b985d9ec0..dec02b8bfadc766aa96bc76aa6130be9ca82936c 100644 (file)
--- a/System.v
+++ b/System.v
@@ -21,19 +21,22 @@ module InternalRAM(
        input clk,
        input wr, rd);
        
        input clk,
        input wr, rd);
        

-       reg [7:0] ram [8191:0];
+       // synthesis attribute ram_style of reg is block
+       reg [7:0] ram [2047:0];

        
        

-       wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
+       wire decode = address[15:13] == 3'b110;

        reg [7:0] odata;
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
        reg [7:0] odata;
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin

-               if (decode && rd)
-                       odata <= ram[address[12:0]];
-               else if (decode && wr)
-                       ram[address[12:0]] <= data;
+               if (decode)
+               begin
+                       if (wr)
+                               ram[address[10:0]] <= data;
+                       odata <= ram[address[10:0]];
+               end

        end
 endmodule
 
        end
 endmodule
 

diff --git a/rom.hex b/rom.hex
index 6d9f1d9d13f75f3036eb0543c1af21b479ae2c9b..a37d956eab31f36740224981acec1861442a29d3 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -8,15 +8,15 @@ df
 50
 06
 00
 50
 06
 00

-cd
-23
-00

 2a
 b8
 ca
 00
 00
 e2
 2a
 b8
 ca
 00
 00
 e2

+cd
+23
+00

 c3
 0a
 00
 c3
 0a
 00