LD reg, reg

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 5e643e3ee37b317a333fc6d53a40f13725e5f82b..84ccd1ce09d13519dacf7b43f54436d7443833f5 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 9bc60a8bfd2dc67da31b34438ad779e893103f5c..e5a7d35e16262ccfa113e892f147e39f9260adee 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -22,14 +22,18 @@
 `define STATE_WRITEBACK                2'h3
 
 `define INSN_LD_reg_imm8       8'b00xxx110
 `define STATE_WRITEBACK                2'h3
 
 `define INSN_LD_reg_imm8       8'b00xxx110

-`define INSN_imm8_reg_A                3'b111
-`define INSN_imm8_reg_B                3'b000
-`define INSN_imm8_reg_C                3'b001
-`define INSN_imm8_reg_D                3'b010
-`define INSN_imm8_reg_E                3'b011
-`define INSN_imm8_reg_H                3'b100
-`define INSN_imm8_reg_L                3'b101
-`define INSN_imm8_reg_dHL      3'b110
+`define INSN_HALT                              8'b01110110
+`define INSN_LD_HL_reg         8'b01110xxx
+`define INSN_LD_reg_HL         8'b01xxx110
+`define INSN_LD_reg_reg                8'b01xxxxxx
+`define INSN_reg_A             3'b111
+`define INSN_reg_B             3'b000
+`define INSN_reg_C             3'b001
+`define INSN_reg_D             3'b010
+`define INSN_reg_E             3'b011
+`define INSN_reg_H             3'b100
+`define INSN_reg_L             3'b101
+`define INSN_reg_dHL   3'b110

 
 module GBZ80Core(
        input clk,
 
 module GBZ80Core(
        input clk,


@@ -49,6 +53,8 @@ module GBZ80Core(
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
        reg rd = 1, wr = 0, newcycle = 1;
        
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
        reg rd = 1, wr = 0, newcycle = 1;
        

+       reg [7:0] tmp;                                  /* Generic temporary reg. */
+       

        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        


@@ -84,6 +90,7 @@ module GBZ80Core(
                        if (newcycle) begin
                                opcode <= busdata;
                                rdata <= busdata;
                        if (newcycle) begin
                                opcode <= busdata;
                                rdata <= busdata;

+                               newcycle <= 0;

                                cycle <= 0;
                        end else
                                if (rd) rdata <= busdata;
                                cycle <= 0;
                        end else
                                if (rd) rdata <= busdata;


@@ -104,12 +111,11 @@ module GBZ80Core(
                                0:      begin
                                                `EXEC_INC_PC;
                                                `EXEC_NEXTADDR_PCINC;
                                0:      begin
                                                `EXEC_INC_PC;
                                                `EXEC_NEXTADDR_PCINC;

-                                               newcycle <= 0;

                                                rd <= 1;
                                        end
                                1: begin
                                                `EXEC_INC_PC;
                                                rd <= 1;
                                        end
                                1: begin
                                                `EXEC_INC_PC;

-                                               if (opcode[5:3] == `INSN_imm8_reg_dHL) begin
+                                               if (opcode[5:3] == `INSN_reg_dHL) begin

                                                        address <= {registers[`REG_H], registers[`REG_L]};
                                                        wdata <= rdata;
                                                        rd <= 0;
                                                        address <= {registers[`REG_H], registers[`REG_L]};
                                                        wdata <= rdata;
                                                        rd <= 0;


@@ -123,6 +129,28 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

+                       `INSN_HALT: begin
+                               /* XXX UNIMP */
+                       end
+                       `INSN_LD_HL_reg: begin
+                               /* XXX UNIMP */
+                       end
+                       `INSN_LD_reg_HL: begin
+                               /* XXX UNIMP */
+                       end
+                       `INSN_LD_reg_reg: begin
+                               `EXEC_INC_PC;
+                               `EXEC_NEWCYCLE;
+                               case (opcode[2:0])
+                               `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
+                               `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
+                               `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
+                               `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
+                               `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
+                               `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
+                               `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
+                               endcase
+                       end

                        endcase
                        state <= `STATE_WRITEBACK;
                end
                        endcase
                        state <= `STATE_WRITEBACK;
                end


@@ -132,17 +160,37 @@ module GBZ80Core(
                                        case (cycle)
                                        0: cycle <= 1;
                                        1: case (opcode[5:3])
                                        case (cycle)
                                        0: cycle <= 1;
                                        1: case (opcode[5:3])

-                                               `INSN_imm8_reg_A:       begin registers[`REG_A] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_B:       begin registers[`REG_B] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_C:       begin registers[`REG_C] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_D:       begin registers[`REG_D] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_E:       begin registers[`REG_E] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_H:       begin registers[`REG_H] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_L:       begin registers[`REG_L] <= rdata; cycle <= 0; end
-                                               `INSN_imm8_reg_dHL:     cycle <= 2;
+                                               `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
+                                               `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
+                                               `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end
+                                               `INSN_reg_D:    begin registers[`REG_D] <= rdata; cycle <= 0; end
+                                               `INSN_reg_E:    begin registers[`REG_E] <= rdata; cycle <= 0; end
+                                               `INSN_reg_H:    begin registers[`REG_H] <= rdata; cycle <= 0; end
+                                               `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
+                                               `INSN_reg_dHL:  cycle <= 2;

                                                endcase
                                        2: cycle <= 0;
                                        endcase
                                                endcase
                                        2: cycle <= 0;
                                        endcase

+                               `INSN_HALT: begin
+                                       /* XXX UNIMP */
+                               end
+                               `INSN_LD_HL_reg: begin
+                                       /* XXX UNIMP */
+                               end
+                               `INSN_LD_reg_HL: begin
+                                       /* XXX UNIMP */
+                               end
+                               `INSN_LD_reg_reg: begin
+                                       case (opcode[5:3])
+                                       `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
+                                       `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
+                                       `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
+                                       `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
+                                       `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
+                                       `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
+                                       `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                                       endcase
+                               end

                        endcase
                        state <= `STATE_FETCH;
                end
                        endcase
                        state <= `STATE_FETCH;
                end

diff --git a/rom.hex b/rom.hex
index 61c700d20f39133cdde9afae732f9c4e36776577..7894cdc24084f0f1a45310572bcdb42a6b896b70 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -1,9 +1,8 @@
-// LD (HL), 05h
-36
-05
-// LD H, 12h
-26
+// LD A, 12h
+3E

 12
 12

+// LD H, A
+67

 // LD L, 34h
 2E
 34
 // LD L, 34h
 2E
 34