Cut 1 at button integration

diff --git a/Buttons.v b/Buttons.v
index 6caecd64e164cb987ef340a34618518ec5899eb1..4d8a171613ad4a8d703c1dcf95e52496db4bc702 100644 (file)
--- a/Buttons.v
+++ b/Buttons.v
@@ -8,23 +8,28 @@ module Buttons(
        input rd,
        input [15:0] addr,
        inout [7:0] data,
        input rd,
        input [15:0] addr,
        inout [7:0] data,

-       input [7:0] buttons
+       input [7:0] buttons,

        output reg int
        );
 
        output reg int
        );
 

+       reg rdlatch;
+       reg [15:0] addrlatch;
+

        reg [7:0] p1;
        reg [3:0] oldp1013;
 
        reg [7:0] p1;
        reg [3:0] oldp1013;
 

-       assign data = (rd && (addr == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
+       assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;

 
        wire p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) | (p1[5] ? 4'b1111 : ~buttons[7:4]);
 
 
        wire p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) | (p1[5] ? 4'b1111 : ~buttons[7:4]);
 

-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin

                if(wr) begin
                        case(addr)
                        `ADDR_P1: p1[5:4] <= data[5:4];
                        endcase
                end
                if(wr) begin
                        case(addr)
                        `ADDR_P1: p1[5:4] <= data[5:4];
                        endcase
                end

+               rdlatch <= rd;
+               addrlatch <= addr;

                p1[3:0] <= p1013;
                oldp1013 <= p1013;
                int <= | (oldp1013 & (oldp1013 ^ p1013));
                p1[3:0] <= p1013;
                oldp1013 <= p1013;
                int <= | (oldp1013 & (oldp1013 ^ p1013));

diff --git a/CoreTop.prj b/CoreTop.prj
index 2b334db738ec1a65f7415cb4e7a45d9aac4f7ab0..0df5890537898d3959f693b9fb54a2621fb2bc43 100644 (file)
--- a/CoreTop.prj
+++ b/CoreTop.prj
@@ -11,3 +11,4 @@ verilog work "pixDCM.v"
 verilog work "Sound1.v"
 verilog work "Sound2.v"
 verilog work "Soundcore.v"
 verilog work "Sound1.v"
 verilog work "Sound2.v"
 verilog work "Soundcore.v"

+verilog work "Buttons.v"

diff --git a/Makefile b/Makefile
index 40ea54287cffa8013f51e1dc817dba3ca6879792..f42e5b99520a30ccd94163f5a48b78a9e71c77fb 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 VLOGS = 7seg.v Framebuffer.v GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
 VLOGS = 7seg.v Framebuffer.v GBZ80Core.v Interrupt.v LCDC.v Sound1.v \

-       Sound2.v Soundcore.v System.v Timer.v Uart.v
+       Sound2.v Soundcore.v System.v Timer.v Uart.v  Buttons.v

 
 VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \
        insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v insn_ret-retcc.v \
 
 VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \
        insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v insn_ret-retcc.v \

diff --git a/System.v b/System.v
index 62f976be7dc3d4f8062de7ad4c07d88131d435a4..931e90029c7c2c438fed2c2a7c6726baf7e4c008 100644 (file)
--- a/System.v
+++ b/System.v
@@ -262,7 +262,7 @@ module CoreTop(
        wire [7:0] data [1:0];
        wire wr [1:0], rd [1:0];
        
        wire [7:0] data [1:0];
        wire wr [1:0], rd [1:0];
        

-       wire irq, tmrirq, lcdcirq, vblankirq;
+       wire irq, tmrirq, lcdcirq, vblankirq, btnirq;

        wire [7:0] jaddr;
        wire [1:0] state;
        wire ack;
        wire [7:0] jaddr;
        wire [1:0] state;
        wire ack;


@@ -357,6 +357,16 @@ module CoreTop(
                .ledout(leds),
                .switches(switches)
                );
                .ledout(leds),
                .switches(switches)
                );

+       
+       Buttons ass(
+               .core_clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .int(btnirq),
+               .buttons(switches)
+               );

 
        AddrMon amon(
                .clk(clk), 
 
        AddrMon amon(
                .clk(clk), 


@@ -415,7 +425,7 @@ module CoreTop(
                .lcdc(lcdcirq),
                .tovf(tmrirq),
                .serial(1'b0),
                .lcdc(lcdcirq),
                .tovf(tmrirq),
                .serial(1'b0),

-               .buttons(1'b0),
+               .buttons(btnirq),

                .master(irq),
                .ack(ack),
                .jaddr(jaddr));
                .master(irq),
                .ack(ack),
                .jaddr(jaddr));

diff --git a/binwire.c b/binwire.c
index 101b5c10bf172d7d90d399f3d59fba7ee8872306..cef0924294a27630901af44fcb23142dc829f843 100644 (file)
--- a/binwire.c
+++ b/binwire.c
@@ -7,10 +7,13 @@
 
 void dowrite(char *s, int len)
 {
 
 void dowrite(char *s, int len)
 {

-  int i;
-  for (i=0; i<len; i++)
+  int i = 0;
+  while (i < len)

   {
   {

-    write(1, s+i, 1);
+    int cs = ((len-i) > 1) ? 1 : (len-i);
+    
+    write(1, s+i, cs);
+    i += cs;

   }
 }
 
   }
 }