module ROM(
input [15:0] address,
inout [7:0] data,
+ input clk,
input wr, rd);
reg [7:0] rom [2047:0];
initial $readmemh("rom.hex", rom);
wire decode = address[15:13] == 0;
- reg [7:0] odata;
- wire idata = data;
+ wire [7:0] odata = rom[address[11:0]];
assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-
- always @(posedge rd)
- if (decode)
- odata <= rom[address];
+ //assign data = rd ? odata : 8'bzzzzzzzz;
endmodule
module InternalRAM(
wire idata = data;
assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
- reg [13:0] diq;
- initial
- for (diq = 0; diq < 8191; diq = diq + 1)
- ram[diq] = 8'h43;
-
always @(negedge clk)
begin
if (decode && rd)
odata <= ram[address[12:0]];
- if (decode && wr)
+ else if (decode && wr)
ram[address[12:0]] <= data;
end
endmodule
-module TestBench();
- reg clk = 0;
+//module Switches(
+// input [15:0] address,
+// inout [7:0] data,
+// input clk,
+// input wr, rd,
+// input [7:0] switches,
+// output reg [7:0] ledout);
+
+// wire decode = address == 16'hFF51;
+// reg [7:0] odata;
+// wire idata = data;
+// assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+// always @(negedge clk)
+// begin
+// if (decode && rd)
+// odata <= switches;
+// else if (decode && wr)
+// ledout <= data;
+// end
+//endmodule
+
+module CoreTop(
+ input iclk,
+ output wire [7:0] leds,
+ output serio);
+
+ wire clk;
+ IBUFG ibuf (.O(clk), .I(iclk));
+
wire [15:0] addr;
wire [7:0] data;
wire wr, rd;
- always #10 clk <= ~clk;
+ wire [7:0] swleds;
+
+ assign leds = clk?{rd,wr,addr[5:0]}:data[7:0];
+
GBZ80Core core(
.clk(clk),
.busaddress(addr),
.busrd(rd));
ROM rom(
- .address(addr),
- .data(data),
- .wr(wr),
- .rd(rd));
-
- InternalRAM ram(
.address(addr),
.data(data),
.clk(clk),
.wr(wr),
.rd(rd));
+
+ assign serio = 0;
endmodule
+
+//module TestBench();
+// reg clk = 0;
+// wire [15:0] addr;
+// wire [7:0] data;
+// wire wr, rd;
+
+// wire [7:0] leds;
+// wire [7:0] switches;
+
+// always #10 clk <= ~clk;
+// GBZ80Core core(
+// .clk(clk),
+// .busaddress(addr),
+// .busdata(data),
+// .buswr(wr),
+// .busrd(rd));
+
+// ROM rom(
+// .clk(clk),
+// .address(addr),
+// .data(data),
+// .wr(wr),
+// .rd(rd));
+
+// InternalRAM ram(
+// .address(addr),
+// .data(data),
+// .clk(clk),
+// .wr(wr),
+// .rd(rd));
+
+// wire serio;
+// UART uart(
+// .addr(addr),
+// .data(data),
+// .clk(clk),
+// .wr(wr),
+// .rd(rd),
+// .serial(serio));
+
+// Switches sw(
+// .clk(clk),
+// .address(addr),
+// .data(data),
+// .wr(wr),
+// .rd(rd),
+// .switches(switches),
+// .leds(leds));
+//endmodule
--- /dev/null
+`define IN_CLK 8400000
+`define OUT_CLK 9600
+`define CLK_DIV `IN_CLK / `OUT_CLK
+`define MMAP_ADDR 16'hFF50
+
+module UART(
+ input clk,
+ input wr,
+ input rd,
+ input [15:0] addr,
+ input [7:0] data,
+ output reg serial);
+
+ reg [7:0] data_stor = 0;
+ reg [15:0] clkdiv = 0;
+ reg have_data = 0;
+ reg data_end = 0;
+ reg [3:0] diqing = 4'b0000;
+
+ wire new = (wr) && (!have_data) && (addr == `MMAP_ADDR);
+
+ always @ (negedge clk)
+ begin
+`define FUQING 4'b1010
+ /* deal with diqing */
+ if(new) begin
+ data_stor <= ~data;
+ have_data <= 1;
+ diqing <= 4'b0000;
+ end else if (clkdiv == 0) begin
+ diqing <= diqing + 1;
+ if (have_data)
+ case (diqing)
+ 4'b0000: serial <= 1;
+ 4'b0001: serial <= data_stor[0];
+ 4'b0010: serial <= data_stor[1];
+ 4'b0011: serial <= data_stor[2];
+ 4'b0100: serial <= data_stor[3];
+ 4'b0101: serial <= data_stor[4];
+ 4'b0110: serial <= data_stor[5];
+ 4'b0111: serial <= data_stor[6];
+ 4'b1000: serial <= data_stor[7];
+ 4'b1001: serial <= 0;
+ 4'b1010: have_data <= 0;
+ default: $stop;
+ endcase
+ end
+
+ /* deal with clkdiv */
+ if((new && !have_data) || clkdiv == `CLK_DIV)
+ clkdiv <= 0;
+ else
+ clkdiv <= clkdiv + 1;
+ end
+endmodule
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