]> Joshua Wise's Git repositories - fpgaboy.git/commitdiff
Fix stupid ethernet bug
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 27 May 2008 04:20:08 +0000 (00:20 -0400)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 27 May 2008 04:20:08 +0000 (00:20 -0400)
Ethernet.v

index bd3fdc734dcc87faacefedec32e1936babc96827..56123c09d251530f11b4858277a9c90805f9486e 100644 (file)
@@ -40,7 +40,7 @@ module Ethernet (
        EthModRam txram(
                .wdata(data),
                .waddr(txwraddr),
-               .wr(wr && state == 2'b10 && addr == `ADDR_ETH),
+               .wr(wr && txstate == 2'b10 && addr == `ADDR_ETH),
                .wrclk(clk),
                .rdata(txhwdata),
                .raddr(txhwaddr),
@@ -82,7 +82,7 @@ module Ethernet (
                rdlatch <= rd;
                
                if (rd && addr == `ADDR_ETH_STATUS)
-                       odata <= {state,4'b0,rxpktrdy,txbusy};
+                       odata <= {txstate,4'b0,rxpktrdy,txbusy};
                else if (wr && addr == `ADDR_ETH_STATUS) begin          /* Reset the state machines. */
                        rxstate <= 2'b00;
                        txstate <= 2'b00;
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