PUSH and POP work

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 5a47155ec16ce79f541ac5154e5b64947b0b0e51..7770eb008676e674792cd2feea4e53b9fad09ccc 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index fa9ed0bef538de32f697ae5cd7a64e505cb843c4..cb80cb8fcfe008cd0a85c16dc8e9a796fc1acc13 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -28,6 +28,8 @@
 `define INSN_LD_reg_reg                8'b01xxxxxx
 `define INSN_LD_reg_imm16      8'b00xx0001
 `define INSN_LD_SP_HL          8'b11111001
+`define INSN_PUSH_reg          8'b11xx0101
+`define INSN_POP_reg           8'b11xx0001
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 `define INSN_reg_C             3'b001
@@ -40,6 +42,10 @@
 `define INSN_reg16_DE  2'b01
 `define INSN_reg16_HL  2'b10
 `define INSN_reg16_SP  2'b11
+`define INSN_stack_AF  2'b11
+`define INSN_stack_BC  2'b00
+`define INSN_stack_DE  2'b01
+`define INSN_stack_HL  2'b10
 module GBZ80Core(
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
@@ -101,6 +107,10 @@ module GBZ80Core(
                                if (rd) rdata <= busdata;
                        buswr <= 0;
                        busrd <= 0;
+                       wr <= 0;
+                       rd <= 0;
+                       address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
+                       wdata <= 8'bxxxxxxxx;
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
@@ -163,7 +173,7 @@ module GBZ80Core(
                                case(cycle)
                                0: begin
                                                address <= {registers[`REG_H], registers[`REG_L]};
-                                               wr <= 0; rd <= 1;
+                                               rd <= 1;
                                        end
                                1: begin
                                                tmp <= rdata;
@@ -202,8 +212,6 @@ module GBZ80Core(
                        `INSN_LD_SP_HL: begin
                                case (cycle)
                                0:      begin
-                                               rd <= 0;
-                                               address <= 16'bxxxxxxxxxxxxxxxx;
                                                tmp <= registers[`REG_H];
                                        end
                                1:      begin
@@ -213,6 +221,51 @@ module GBZ80Core(
                                        end
                                endcase
                        end
+                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
+                               case (cycle)
+                               0: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: wdata <= registers[`REG_A];
+                                               `INSN_stack_BC: wdata <= registers[`REG_B];
+                                               `INSN_stack_DE: wdata <= registers[`REG_D];
+                                               `INSN_stack_HL: wdata <= registers[`REG_H];
+                                               endcase
+                                       end
+                               1: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: wdata <= registers[`REG_F];
+                                               `INSN_stack_BC: wdata <= registers[`REG_C];
+                                               `INSN_stack_DE: wdata <= registers[`REG_E];
+                                               `INSN_stack_HL: wdata <= registers[`REG_L];
+                                               endcase
+                                       end
+                               2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
+                               3: begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
+                               case (cycle)
+                               0: begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               1: begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               2: begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
                        default:
                                $stop;
                        endcase
@@ -308,6 +361,51 @@ module GBZ80Core(
                                        end
                                endcase
                        end
+                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
+                               case (cycle)
+                               0: begin
+                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               cycle <= 1;
+                                       end
+                               1:      begin
+                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               cycle <= 2;
+                                       end
+                               2:      cycle <= 3;
+                               3:      cycle <= 0;
+                               endcase
+                       end
+                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
+                               case (cycle)
+                               0:      begin
+                                               cycle <= 1;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                       end
+                               1:      begin
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: registers[`REG_F] <= rdata;
+                                               `INSN_stack_BC: registers[`REG_C] <= rdata;
+                                               `INSN_stack_DE: registers[`REG_E] <= rdata;
+                                               `INSN_stack_HL: registers[`REG_L] <= rdata;
+                                               endcase
+                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                               cycle <= 2;
+                                       end
+                               2:      begin
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: registers[`REG_A] <= rdata;
+                                               `INSN_stack_BC: registers[`REG_B] <= rdata;
+                                               `INSN_stack_DE: registers[`REG_D] <= rdata;
+                                               `INSN_stack_HL: registers[`REG_H] <= rdata;
+                                               endcase
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end     
                        endcase
                        state <= `STATE_FETCH;
                end

diff --git a/rom.hex b/rom.hex
index a90b9628a2631fdd3bf3df751942028e4492d2df..00214cd267f18bfa9ba1454a53e6e983645293b1 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -4,8 +4,8 @@
 01
 // LD SP, HL
 F9
-// LD B, (HL)
-46
+// POP BC
+C1
 // LD A, 12h
 3E
 12
@@ -20,4 +20,5 @@ F9
 76
 
 @100
-56
\ No newline at end of file
+00
+56