Get it running on the board.

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 51f6fcad273d4fd378cc27f87a5a6512f9757160..c8729d3c44091249ec219e81ba61c4822fa6ef2b 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index afa4495c2ba6f7a1e28cd79d4b04676b6df5646c..fc773779ceaae29f3206f94ff67aa8cd6d7e75be 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -101,19 +101,28 @@ module GBZ80Core(
                registers[ 9] <= 0;
                registers[10] <= 0;
                registers[11] <= 0;
                registers[ 9] <= 0;
                registers[10] <= 0;
                registers[11] <= 0;

+               ie <= 0;
+               rd <= 1;
+               wr <= 0;
+               newcycle <= 1;
+               state <= 0;
+               cycle <= 0;

        end
 
        always @(posedge clk)
                case (state)
                `STATE_FETCH: begin
        end
 
        always @(posedge clk)
                case (state)
                `STATE_FETCH: begin

-                       if (wr)
-                               buswdata <= wdata;
-                       if (newcycle)
+                       if (newcycle) begin

                                busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
                                busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};

-                       else
+                               buswr <= 0;
+                               busrd <= 1;
+                       end else begin

                                busaddress <= address;
                                busaddress <= address;

-                       buswr <= wr;
-                       busrd <= rd;
+                               buswr <= wr;
+                               busrd <= rd;
+                               if (wr)
+                                       buswdata <= wdata;
+                       end

                        state <= `STATE_DECODE;
                end
                `STATE_DECODE: begin
                        state <= `STATE_DECODE;
                end
                `STATE_DECODE: begin


@@ -122,8 +131,10 @@ module GBZ80Core(
                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;
                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;

-                       end else
+                       end else begin

                                if (rd) rdata <= busdata;
                                if (rd) rdata <= busdata;

+                               cycle <= cycle + 1;
+                       end

                        buswr <= 0;
                        busrd <= 0;
                        wr <= 0;
                        buswr <= 0;
                        busrd <= 0;
                        wr <= 0;


@@ -421,32 +432,29 @@ module GBZ80Core(
                        casex (opcode)
                        `INSN_LD_reg_imm8:
                                case (cycle)
                        casex (opcode)
                        `INSN_LD_reg_imm8:
                                case (cycle)

-                               0:      cycle <= 1;
+                               0:      begin end

                                1:      case (opcode[5:3])
                                1:      case (opcode[5:3])

-                                       `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
-                                       `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
-                                       `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end
-                                       `INSN_reg_D:    begin registers[`REG_D] <= rdata; cycle <= 0; end
-                                       `INSN_reg_E:    begin registers[`REG_E] <= rdata; cycle <= 0; end
-                                       `INSN_reg_H:    begin registers[`REG_H] <= rdata; cycle <= 0; end
-                                       `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
-                                       `INSN_reg_dHL:  cycle <= 2;
+                                       `INSN_reg_A:    begin registers[`REG_A] <= rdata; end
+                                       `INSN_reg_B:    begin registers[`REG_B] <= rdata; end
+                                       `INSN_reg_C:    begin registers[`REG_C] <= rdata; end
+                                       `INSN_reg_D:    begin registers[`REG_D] <= rdata; end
+                                       `INSN_reg_E:    begin registers[`REG_E] <= rdata; end
+                                       `INSN_reg_H:    begin registers[`REG_H] <= rdata; end
+                                       `INSN_reg_L:    begin registers[`REG_L] <= rdata; end
+                                       `INSN_reg_dHL:  begin /* Go off to cycle 2 */ end

                                        endcase
                                        endcase

-                               2:      cycle <= 0;
+                               2:      begin end

                                endcase
                        `INSN_HALT: begin
                                /* Nothing needs happen here. */
                                /* XXX Interrupts needed for HALT. */
                        end
                        `INSN_LD_HL_reg: begin
                                endcase
                        `INSN_HALT: begin
                                /* Nothing needs happen here. */
                                /* XXX Interrupts needed for HALT. */
                        end
                        `INSN_LD_HL_reg: begin

-                               case (cycle)
-                               0:      cycle <= 1;
-                               1:      cycle <= 0;
-                               endcase
+                               /* Nothing of interest here */

                        end
                        `INSN_LD_reg_HL: begin
                                case (cycle)
                        end
                        `INSN_LD_reg_HL: begin
                                case (cycle)

-                               0:      cycle <= 1;
+                               0:      begin end

                                1:      begin
                                                case (opcode[5:3])
                                                `INSN_reg_A:    registers[`REG_A] <= tmp;
                                1:      begin
                                                case (opcode[5:3])
                                                `INSN_reg_A:    registers[`REG_A] <= tmp;


@@ -457,7 +465,6 @@ module GBZ80Core(
                                                `INSN_reg_H:    registers[`REG_H] <= tmp;
                                                `INSN_reg_L:    registers[`REG_L] <= tmp;
                                                endcase
                                                `INSN_reg_H:    registers[`REG_H] <= tmp;
                                                `INSN_reg_L:    registers[`REG_L] <= tmp;
                                                endcase

-                                               cycle <= 0;

                                        end
                                endcase
                        end
                                        end
                                endcase
                        end


@@ -474,7 +481,7 @@ module GBZ80Core(
                        end
                        `INSN_LD_reg_imm16: begin
                                case (cycle)
                        end
                        `INSN_LD_reg_imm16: begin
                                case (cycle)

-                               0:      cycle <= 1;
+                               0:      begin /* */ end

                                1:      begin
                                                case (opcode[5:4])
                                                `INSN_reg16_BC: registers[`REG_C] <= rdata;
                                1:      begin
                                                case (opcode[5:4])
                                                `INSN_reg16_BC: registers[`REG_C] <= rdata;


@@ -482,7 +489,6 @@ module GBZ80Core(
                                                `INSN_reg16_HL: registers[`REG_L] <= rdata;
                                                `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
                                                endcase
                                                `INSN_reg16_HL: registers[`REG_L] <= rdata;
                                                `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
                                                endcase

-                                               cycle <= 2;

                                        end
                                2: begin
                                                case (opcode[5:4])
                                        end
                                2: begin
                                                case (opcode[5:4])


@@ -491,45 +497,29 @@ module GBZ80Core(
                                                `INSN_reg16_HL: registers[`REG_H] <= rdata;
                                                `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
                                                endcase
                                                `INSN_reg16_HL: registers[`REG_H] <= rdata;
                                                `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
                                                endcase

-                                               cycle <= 0;

                                        end
                                endcase
                        end
                        `INSN_LD_SP_HL: begin
                                case (cycle)
                                        end
                                endcase
                        end
                        `INSN_LD_SP_HL: begin
                                case (cycle)

-                               0: begin
-                                               cycle <= 1;
-                                               registers[`REG_SPH] <= tmp;
-                                       end
-                               1: begin
-                                               cycle <= 0;
-                                               registers[`REG_SPL] <= tmp;
-                                       end
+                               0:      registers[`REG_SPH] <= tmp;
+                               1: registers[`REG_SPL] <= tmp;

                                endcase
                        end
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)
                                endcase
                        end
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)

-                               0: begin
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                                               cycle <= 1;
-                                       end
-                               1:      begin
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                                               cycle <= 2;
-                                       end
-                               2:      cycle <= 3;
-                               3:      cycle <= 0;
+                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                               1:      {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                               2:      begin /* type F */ end
+                               3:      begin /* type F */ end

                                endcase
                        end
                        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                                case (cycle)
                                endcase
                        end
                        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                                case (cycle)

-                               0:      begin
-                                               cycle <= 1;
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
-                                       end
+                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                               {registers[`REG_SPH],registers[`REG_SPL]} + 1;

                                1:      begin
                                                case (opcode[5:4])
                                                `INSN_stack_AF: registers[`REG_F] <= rdata;
                                1:      begin
                                                case (opcode[5:4])
                                                `INSN_stack_AF: registers[`REG_F] <= rdata;


@@ -539,7 +529,6 @@ module GBZ80Core(
                                                endcase
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                                endcase
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 1;

-                                               cycle <= 2;

                                        end
                                2:      begin
                                                case (opcode[5:4])
                                        end
                                2:      begin
                                                case (opcode[5:4])


@@ -548,25 +537,20 @@ module GBZ80Core(
                                                `INSN_stack_DE: registers[`REG_D] <= rdata;
                                                `INSN_stack_HL: registers[`REG_H] <= rdata;
                                                endcase
                                                `INSN_stack_DE: registers[`REG_D] <= rdata;
                                                `INSN_stack_HL: registers[`REG_H] <= rdata;
                                                endcase

-                                               cycle <= 0;

                                        end
                                endcase
                        end
                        `INSN_LDH_AC: begin
                                case (cycle)
                                        end
                                endcase
                        end
                        `INSN_LDH_AC: begin
                                case (cycle)

-                               0:      cycle <= 1;
-                               1: begin
-                                               cycle <= 0;
-                                               if (opcode[4])
-                                                       registers[`REG_A] <= rdata;
-                                       end
+                               0:      begin /* Type F */ end
+                               1:      if (opcode[4])
+                                               registers[`REG_A] <= rdata;

                                endcase
                        end
                        `INSN_LDx_AHL: begin
                                case (cycle)
                                endcase
                        end
                        `INSN_LDx_AHL: begin
                                case (cycle)

-                               0:      cycle <= 1;
+                               0:      begin /* Type F */ end

                                1:      begin
                                1:      begin

-                                               cycle <= 0;

                                                if (opcode[3])
                                                        registers[`REG_A] <= rdata;
                                                {registers[`REG_H],registers[`REG_L]} <=
                                                if (opcode[3])
                                                        registers[`REG_A] <= rdata;
                                                {registers[`REG_H],registers[`REG_L]} <=


@@ -579,7 +563,6 @@ module GBZ80Core(
                        `INSN_ALU8: begin
                                if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
                                        /* Sit on our asses. */
                        `INSN_ALU8: begin
                                if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
                                        /* Sit on our asses. */

-                                       cycle <= 1;

                                end else begin          /* Actually do the computation! */
                                        case (opcode[5:3])
                                        `INSN_alu_ADD: begin
                                end else begin          /* Actually do the computation! */
                                        case (opcode[5:3])
                                        `INSN_alu_ADD: begin


@@ -639,29 +622,19 @@ module GBZ80Core(
                        `INSN_NOP: begin /* NOP! */ end
                        `INSN_RST: begin
                                case (cycle)
                        `INSN_NOP: begin /* NOP! */ end
                        `INSN_RST: begin
                                case (cycle)

-                               0:      cycle <= 1;
-                               1:      cycle <= 2;
-                               2:      cycle <= 3;
-                               3:      begin
-                                               cycle <= 0;
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]}-2;
-                                       end
+                               0:      begin /* type F */ end
+                               1:      begin /* type F */ end
+                               2:      begin /* type F */ end
+                               3:      {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                               {registers[`REG_SPH],registers[`REG_SPL]}-2;

                                endcase
                        end
                        `INSN_RET: begin
                                case (cycle)
                                endcase
                        end
                        `INSN_RET: begin
                                case (cycle)

-                               0:      cycle <= 1;
-                               1:      begin
-                                               cycle <= 2;
-                                               registers[`REG_PCL] <= rdata;
-                                       end
-                               2:      begin
-                                               cycle <= 3;
-                                               registers[`REG_PCH] <= rdata;
-                                       end
+                               0:      begin /* type F */ end
+                               1:      registers[`REG_PCL] <= rdata;
+                               2:      registers[`REG_PCH] <= rdata;

                                3:      begin
                                3:      begin

-                                               cycle <= 0;

                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 2;
                                                if (opcode[4])  /* RETI */
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 2;
                                                if (opcode[4])  /* RETI */


@@ -671,27 +644,15 @@ module GBZ80Core(
                        end
                        `INSN_CALL: begin
                                case (cycle)
                        end
                        `INSN_CALL: begin
                                case (cycle)

-                               0:      cycle <= 1;
-                               1:      begin
-                                               cycle <= 2;
-                                               tmp <= rdata;   // tmp contains newpcl
-                                       end
-                               2:      begin
-                                               cycle <= 3;
-                                               tmp2 <= rdata;  // tmp2 contains newpch
-                                       end
-                               3: begin
-                                               cycle <= 4;
-                                       end
-                               4: begin
-                                               cycle <= 5;
-                                               registers[`REG_PCH] <= tmp2;
-                                       end
+                               0:      begin /* type F */ end
+                               1:      tmp <= rdata;   // tmp contains newpcl
+                               2:      tmp2 <= rdata;  // tmp2 contains newpch
+                               3:      begin /* type F */ end
+                               4:      registers[`REG_PCH] <= tmp2;

                                5: begin
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} - 2;
                                                registers[`REG_PCL] <= tmp;
                                5: begin
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} - 2;
                                                registers[`REG_PCL] <= tmp;

-                                               cycle <= 0;

                                        end
                                endcase
                        end
                                        end
                                endcase
                        end


@@ -764,20 +725,22 @@ endmodule
 //endmodule
 
 module CoreTop(
 //endmodule
 
 module CoreTop(

-       input iclk,
+       input iclk, xtal,

        output wire [7:0] leds,
        output wire [7:0] leds,

-       output serio);
+       output serio,
+       output wire [3:0] digits,
+       output wire [7:0] seven);

        
        wire clk;
        
        wire clk;

-       IBUFG ibuf (.O(clk), .I(iclk));
+       //IBUFG ibuf (.O(clk), .I(iclk));
+       
+       CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));

 
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
        
 
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
        

-       wire [7:0] swleds;
-       
-       assign leds = clk?{rd,wr,addr[5:0]}:data[7:0];
+       assign leds = iclk?{rd,wr,addr[5:0]}:data[7:0];

 
        GBZ80Core core(
                .clk(clk),
 
        GBZ80Core core(
                .clk(clk),


@@ -793,32 +756,39 @@ module CoreTop(
                .wr(wr),
                .rd(rd));
        
                .wr(wr),
                .rd(rd));
        

+       AddrMon amon(
+    .addr(addr), 
+    .clk(xtal), 
+    .digit(digits), 
+    .out(seven)
+    );
+       

        assign serio = 0;
 endmodule
 
        assign serio = 0;
 endmodule
 

-//module TestBench();
-//     reg clk = 0;
-//     wire [15:0] addr;
-//     wire [7:0] data;
-//     wire wr, rd;
+module TestBench();
+       reg clk = 0;
+       wire [15:0] addr;
+       wire [7:0] data;
+       wire wr, rd;

        
 //     wire [7:0] leds;
 //     wire [7:0] switches;
        
        
 //     wire [7:0] leds;
 //     wire [7:0] switches;
        

-//     always #10 clk <= ~clk;
-//     GBZ80Core core(
-//             .clk(clk),
-//             .busaddress(addr),
-//             .busdata(data),
-//             .buswr(wr),
-//             .busrd(rd));
+       always #10 clk <= ~clk;
+       GBZ80Core core(
+               .clk(clk),
+               .busaddress(addr),
+               .busdata(data),
+               .buswr(wr),
+               .busrd(rd));

        
        

-//     ROM rom(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd));
+       ROM rom(
+               .clk(clk),
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd));

        
 //     InternalRAM ram(
 //             .address(addr),
        
 //     InternalRAM ram(
 //             .address(addr),


@@ -844,4 +814,4 @@ endmodule
 //             .rd(rd),
 //             .switches(switches),
 //             .leds(leds));
 //             .rd(rd),
 //             .switches(switches),
 //             .leds(leds));

-//endmodule
+endmodule