Make it easy to see what's going wrong.

diff --git a/LCDC.v b/LCDC.v
index 9cebfd7d161712d690dd561749d1a48b0bdfe135..0e1b569cedce48b5428e95fa1e1fd6bbb2b5e4fd 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -148,14 +148,14 @@ module LCDC(
        wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
        
        always @(negedge clk)
-               if ((vraminuse && ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110)))) || decode_bgmap1) begin
+               if ((vraminuse && ((posx == 1) || (vxpos[2:0] == 3'b110))) || decode_bgmap1) begin
                        tileno <= bgmap1[bgmapaddr_in];
                        if (wr && decode_bgmap1 && ~vraminuse)
                                bgmap1[bgmapaddr_in] <= data;
                end
        
        always @(negedge clk)
-               if ((vraminuse && ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111)))) || decode_tiledata) begin
+               if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_tiledata) begin
                        tilehigh <= tiledatahigh[tileaddr_in];
                        tilelow <= tiledatalow[tileaddr_in];
                        if (wr && addr[0] && decode_tiledata && ~vraminuse)

diff --git a/diag.asm b/diag.asm
index 50cefe73b0dff3747ce10de9d9d98202859e9b01..77c520264a6715e5e1758a334eb0b8b68f0af90b 100644 (file)
--- a/diag.asm
+++ b/diag.asm
@@ -50,59 +50,52 @@ main:
 signon:
        db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
 
+tiles:
+       db %11111111
+       db %11111111
+       db %11000011
+       db %11000011
+       db %11000011
+       db %11000011
+       db %11111111
+       db %11111111
+       
+       db %00000000
+       db %00000000
+       db %00000000
+       db %00000000
+       db %00000000
+       db %00000000
+       db %00000000
+       db %00000000
+
 putscreen:
        ; Wait for vblank
        call .vblwait
 
        ld hl, $8000    ; Copy two tiles.
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
-       ld [hli], a
-       ld [hli], a
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
-       ld [hli], a
-       ld [hli], a
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
-       ld [hli], a
-       ld [hli], a
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
+       ld de, tiles
+       ld c, $10
+.cloop:        push hl
+       ld h, d
+       ld l, e
+       ld a, [hl]
+       inc de
+       pop hl
        ld [hli], a
        ld [hli], a
+       dec c
        xor a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
+       cp c
+       jr nz, .cloop
        
        ld hl, $9800
 .vloop:        call .vblwait
        ld c, $40
-.loop: ld a, $01
-       ld [hli], a
-       xor a
+       ld b, 0
+.loop: inc b
+       ld a, b
+       and $01
        ld [hli], a
        ld a, h
        cp $9C