X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/fe3dc8909a6c72ce4208cb5b8b64bc6b2f8cebd6..e7fb589a21ee26ad897e03cbd0d7a647d9cd97e5:/System.v

diff --git a/System.v b/System.v
index dbcfaa4..cdcee09 100644
--- a/System.v
+++ b/System.v
@@ -15,6 +15,29 @@ module ROM(
 	//assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 
+module MiniRAM(			/* XXX will need to go INSIDE the CPU for when we do DMA */
+	input [15:0] address,
+	inout [7:0] data,
+	input clk,
+	input wr, rd);
+	
+	reg [7:0] ram [127:0];
+	
+	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
+	reg [7:0] odata;
+	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	
+	always @(negedge clk)
+	begin
+		if (decode)	// This has to go this way. The only way XST knows how to do
+		begin				// block ram is chip select, write enable, and always
+			if (wr)		// reading. "else if rd" does not cut it ...
+				ram[address[6:0]] <= data;
+			odata <= ram[address[6:0]];
+		end
+	end
+endmodule
+
 module InternalRAM(
 	input [15:0] address,
 	inout [7:0] data,
@@ -60,7 +83,16 @@ module Switches(
 	end
 endmodule
 
+`ifdef isim
+module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
+endmodule
+`endif
+
 module CoreTop(
+`ifdef isim
+	output reg vgaclk = 0,
+	output reg clk = 0,
+`else
 	input xtal,
 	input [7:0] switches,
 	input [3:0] buttons,
@@ -68,15 +100,31 @@ module CoreTop(
 	output serio,
 	output wire [3:0] digits,
 	output wire [7:0] seven,
+`endif
 	output wire hs, vs,
 	output wire [2:0] r, g,
-	output wire [1:0] b);
+	output wire [1:0] b,
+	output wire soundl, soundr);
+
+`ifdef isim
+	always #62 clk <= ~clk;
+	always #100 vgaclk <= ~vgaclk;
+	
+	Dumpable dump(r,g,b,hs,vs,vgaclk);
 	
+	wire [7:0] leds;
+	wire serio;
+	wire [3:0] digits;
+	wire [7:0] seven;
+	wire [7:0] switches = 8'b0;
+	wire [3:0] buttons = 4'b0;
+`else	
 	wire xtalb, clk, vgaclk;
 	IBUFG iclkbuf(.O(xtalb), .I(xtal));
 	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
 	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
-	
+`endif
+
 	wire [15:0] addr;	
 	wire [7:0] data;
 	wire wr, rd;
@@ -173,6 +221,14 @@ module CoreTop(
 		.wr(wr),
 		.rd(rd)
 		);
+	
+	MiniRAM mram(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd)
+		);
 
 	Timer tmr(
 		.clk(clk),
@@ -192,12 +248,23 @@ module CoreTop(
 		.vblank(vblankirq),
 		.lcdc(lcdcirq),
 		.tovf(tmrirq),
-		.serial(0),
-		.buttons(0),
+		.serial(1'b0),
+		.buttons(1'b0),
 		.master(irq),
 		.jaddr(jaddr));
+	
+	Soundcore sound(
+		.core_clk(clk),
+		.rd(rd),
+		.wr(wr),
+		.addr(addr),
+		.data(data),
+		.snd_data_l(soundl),
+		.snd_data_r(soundr));
 endmodule
 
+`ifdef verilator
+`else
 module TestBench();
 	reg clk = 1;
 	wire [15:0] addr;
@@ -274,3 +341,4 @@ module TestBench();
 		.switches(switches),
 		.ledout(leds));
 endmodule
+`endif