X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/f8db64484a25b6970acb75b35188efd7089e572a..ee31adcb22c5011aeaaa0149ee22fa18e45317a5:/System.v?ds=sidebyside

diff --git a/System.v b/System.v
index 7319ebf..dbcfaa4 100644
--- a/System.v
+++ b/System.v
@@ -6,11 +6,11 @@ module ROM(
 	input clk,
 	input wr, rd);
 
-	reg [7:0] rom [2047:0];
+	reg [7:0] rom [1023:0];
 	initial $readmemh("rom.hex", rom);
 
 	wire decode = address[15:13] == 0;
-	wire [7:0] odata = rom[address[11:0]];
+	wire [7:0] odata = rom[address[10:0]];
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	//assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
@@ -21,12 +21,11 @@ module InternalRAM(
 	input clk,
 	input wr, rd);
 	
-	// synthesis attribute ram_style of reg is block
+	// synthesis attribute ram_style of ram is block
 	reg [7:0] ram [8191:0];
 	
 	wire decode = address[15:13] == 3'b110;
 	reg [7:0] odata;
-	wire idata = data;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
 	always @(negedge clk)
@@ -46,7 +45,7 @@ module Switches(
 	input clk,
 	input wr, rd,
 	input [7:0] switches,
-	output reg [7:0] ledout);
+	output reg [7:0] ledout = 0);
 	
 	wire decode = address == 16'hFF51;
 	reg [7:0] odata;
@@ -68,18 +67,24 @@ module CoreTop(
 	output wire [7:0] leds,
 	output serio,
 	output wire [3:0] digits,
-	output wire [7:0] seven);
+	output wire [7:0] seven,
+	output wire hs, vs,
+	output wire [2:0] r, g,
+	output wire [1:0] b);
+	
+	wire xtalb, clk, vgaclk;
+	IBUFG iclkbuf(.O(xtalb), .I(xtal));
+	CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
+	pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 	
-	wire clk;	
-	CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
-
 	wire [15:0] addr;	
 	wire [7:0] data;
 	wire wr, rd;
 	
-	wire irq, tmrirq;
+	wire irq, tmrirq, lcdcirq, vblankirq;
 	wire [7:0] jaddr;
-
+	wire [1:0] state;
+	
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),
@@ -87,7 +92,8 @@ module CoreTop(
 		.buswr(wr),
 		.busrd(rd),
 		.irq(irq),
-		.jaddr(jaddr));
+		.jaddr(jaddr),
+		.state(state));
 	
 	ROM rom(
 		.address(addr),
@@ -96,13 +102,50 @@ module CoreTop(
 		.wr(wr),
 		.rd(rd));
 	
+	wire lcdhs, lcdvs, lcdclk;
+	wire [2:0] lcdr, lcdg;
+	wire [1:0] lcdb;
+	
+	LCDC lcdc(
+		.addr(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.lcdcirq(lcdcirq),
+		.vblankirq(vblankirq),
+		.lcdclk(lcdclk),
+		.lcdhs(lcdhs),
+		.lcdvs(lcdvs),
+		.lcdr(lcdr),
+		.lcdg(lcdg),
+		.lcdb(lcdb));
+	
+	Framebuffer fb(
+		.lcdclk(lcdclk),
+		.lcdhs(lcdhs),
+		.lcdvs(lcdvs),
+		.lcdr(lcdr),
+		.lcdg(lcdg),
+		.lcdb(lcdb),
+		.vgaclk(vgaclk),
+		.vgahs(hs),
+		.vgavs(vs),
+		.vgar(r),
+		.vgag(g),
+		.vgab(b));
+	
 	AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-	 .freeze(buttons[0])
-    );
+		.addr(addr), 
+		.clk(clk), 
+		.digit(digits), 
+		.out(seven),
+		.freeze(buttons[0]),
+		.periods(
+			(state == 2'b00) ? 4'b0010 :
+			(state == 2'b01) ? 4'b0001 :
+			(state == 2'b10) ? 4'b1000 :
+			                   4'b0100) );
 	 
 	Switches sw(
 		.address(addr),
@@ -115,20 +158,21 @@ module CoreTop(
 		);
 
 	UART nouart (	/* no u */
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+		.clk(clk), 
+		.wr(wr), 
+		.rd(rd), 
+		.addr(addr), 
+		.data(data), 
+		.serial(serio)
+		);
 
-  InternalRAM ram(
+	InternalRAM ram(
 		.address(addr),
 		.data(data),
 		.clk(clk),
 		.wr(wr),
-		.rd(rd));
+		.rd(rd)
+		);
 
 	Timer tmr(
 		.clk(clk),
@@ -136,7 +180,8 @@ module CoreTop(
 		.rd(rd),
 		.addr(addr),
 		.data(data),
-		.irq(tmrirq));
+		.irq(tmrirq)
+		);
 	
 	Interrupt intr(
 		.clk(clk),
@@ -144,8 +189,8 @@ module CoreTop(
 		.wr(wr),
 		.addr(addr),
 		.data(data),
-		.vblank(0),
-		.lcdc(0),
+		.vblank(vblankirq),
+		.lcdc(lcdcirq),
 		.tovf(tmrirq),
 		.serial(0),
 		.buttons(0),
@@ -162,10 +207,10 @@ module TestBench();
 	wire irq, tmrirq;
 	wire [7:0] jaddr;
 	
-//	wire [7:0] leds;
-//	wire [7:0] switches;
+	wire [7:0] leds;
+	wire [7:0] switches;
 	
-	always #10 clk <= ~clk;
+	always #62 clk <= ~clk;
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),
@@ -220,12 +265,12 @@ module TestBench();
 		.master(irq),
 		.jaddr(jaddr));
 	
-//	Switches sw(
-//		.clk(clk),
-//		.address(addr),
-//		.data(data),
-//		.wr(wr),
-//		.rd(rd),
-//		.switches(switches),
-//		.leds(leds));
+	Switches sw(
+		.clk(clk),
+		.address(addr),
+		.data(data),
+		.wr(wr),
+		.rd(rd),
+		.switches(switches),
+		.ledout(leds));
 endmodule