X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/f8db64484a25b6970acb75b35188efd7089e572a..81358c71b258a72a2777bba0a0b4a82a7cae298a:/System.v?ds=sidebyside

diff --git a/System.v b/System.v
index 7319ebf..5d4fbed 100644
--- a/System.v
+++ b/System.v
@@ -46,7 +46,7 @@ module Switches(
 	input clk,
 	input wr, rd,
 	input [7:0] switches,
-	output reg [7:0] ledout);
+	output reg [7:0] ledout = 0);
 	
 	wire decode = address == 16'hFF51;
 	reg [7:0] odata;
@@ -162,8 +162,8 @@ module TestBench();
 	wire irq, tmrirq;
 	wire [7:0] jaddr;
 	
-//	wire [7:0] leds;
-//	wire [7:0] switches;
+	wire [7:0] leds;
+	wire [7:0] switches;
 	
 	always #10 clk <= ~clk;
 	GBZ80Core core(
@@ -220,12 +220,12 @@ module TestBench();
 		.master(irq),
 		.jaddr(jaddr));
 	
-//	Switches sw(
-//		.clk(clk),
-//		.address(addr),
-//		.data(data),
-//		.wr(wr),
-//		.rd(rd),
-//		.switches(switches),
-//		.leds(leds));
+	Switches sw(
+		.clk(clk),
+		.address(addr),
+		.data(data),
+		.wr(wr),
+		.rd(rd),
+		.switches(switches),
+		.ledout(leds));
 endmodule