X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/f8db64484a25b6970acb75b35188efd7089e572a..6c46357c6f1bfeefc3a9f85aed03f94e923d09f1:/System.v diff --git a/System.v b/System.v index 7319ebf..4081771 100644 --- a/System.v +++ b/System.v @@ -26,7 +26,6 @@ module InternalRAM( wire decode = address[15:13] == 3'b110; reg [7:0] odata; - wire idata = data; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; always @(negedge clk) @@ -46,7 +45,7 @@ module Switches( input clk, input wr, rd, input [7:0] switches, - output reg [7:0] ledout); + output reg [7:0] ledout = 0); wire decode = address == 16'hFF51; reg [7:0] odata; @@ -72,6 +71,9 @@ module CoreTop( wire clk; CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk)); + + wire cclk; + IBUFG ibuf (.O(cclk), .I(switches[0])); wire [15:0] addr; wire [7:0] data; @@ -79,15 +81,17 @@ module CoreTop( wire irq, tmrirq; wire [7:0] jaddr; + wire [1:0] state; GBZ80Core core( - .clk(clk), + .clk(cclk), .busaddress(addr), .busdata(data), .buswr(wr), .busrd(rd), .irq(irq), - .jaddr(jaddr)); + .jaddr(jaddr), + .state(state)); ROM rom( .address(addr), @@ -97,12 +101,16 @@ module CoreTop( .rd(rd)); AddrMon amon( - .addr(addr), - .clk(clk), - .digit(digits), - .out(seven), - .freeze(buttons[0]) - ); + .addr(addr), + .clk(clk), + .digit(digits), + .out(seven), + .freeze(buttons[0]), + .periods( + (state == 2'b00) ? 4'b1000 : + (state == 2'b01) ? 4'b0100 : + (state == 2'b10) ? 4'b0010 : + 4'b0001) ); Switches sw( .address(addr), @@ -111,24 +119,25 @@ module CoreTop( .wr(wr), .rd(rd), .ledout(leds), - .switches(switches) + .switches({switches[7:1],1'b0}) ); UART nouart ( /* no u */ - .clk(clk), - .wr(wr), - .rd(rd), - .addr(addr), - .data(data), - .serial(serio) - ); + .clk(clk), + .wr(wr), + .rd(rd), + .addr(addr), + .data(data), + .serial(serio) + ); - InternalRAM ram( + InternalRAM ram( .address(addr), .data(data), .clk(clk), .wr(wr), - .rd(rd)); + .rd(rd) + ); Timer tmr( .clk(clk), @@ -136,7 +145,8 @@ module CoreTop( .rd(rd), .addr(addr), .data(data), - .irq(tmrirq)); + .irq(tmrirq) + ); Interrupt intr( .clk(clk), @@ -162,8 +172,8 @@ module TestBench(); wire irq, tmrirq; wire [7:0] jaddr; -// wire [7:0] leds; -// wire [7:0] switches; + wire [7:0] leds; + wire [7:0] switches; always #10 clk <= ~clk; GBZ80Core core( @@ -220,12 +230,12 @@ module TestBench(); .master(irq), .jaddr(jaddr)); -// Switches sw( -// .clk(clk), -// .address(addr), -// .data(data), -// .wr(wr), -// .rd(rd), -// .switches(switches), -// .leds(leds)); + Switches sw( + .clk(clk), + .address(addr), + .data(data), + .wr(wr), + .rd(rd), + .switches(switches), + .ledout(leds)); endmodule