X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/f2e0471561f022000caa932bbe012edde964b6eb..5bac4cf0a60acac6826eb3215e1526d48ba8f7ac:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 738bf91..f438339 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -1,31 +1,79 @@
-`define REG_A 0
-`define REG_B 1
-`define REG_C 2
-`define REG_D 3
-`define REG_E 4
-`define REG_F 5
-`define REG_H 6
-`define REG_L 7
-`define REG_SPH 8
-`define REG_SPL 9
-`define REG_PCH 10
-`define REG_PCL 11
+`define REG_A	0
+`define REG_B	1
+`define REG_C	2
+`define REG_D	3
+`define REG_E	4
+`define REG_F	5
+`define REG_H	6
+`define REG_L	7
+`define REG_SPH	8
+`define REG_SPL	9
+`define REG_PCH	10
+`define REG_PCL	11
 
-`define FLAG_Z 8'b10000000
-`define FLAG_N 8'b01000000
-`define FLAG_H 8'b00100000
-`define FLAG_C 8'b00010000
+`define _A	registers[`REG_A]
+`define _B	registers[`REG_B]
+`define _C	registers[`REG_C]
+`define _D	registers[`REG_D]
+`define _E	registers[`REG_E]
+`define _F	registers[`REG_F]
+`define _H	registers[`REG_H]
+`define _L	registers[`REG_L]
+`define _SPH	registers[`REG_SPH]
+`define _SPL	registers[`REG_SPL]
+`define _PCH	registers[`REG_PCH]
+`define _PCL	registers[`REG_PCL]
+`define _AF	{`_A, `_F}
+`define _BC	{`_B, `_C}
+`define _DE	{`_D, `_E}
+`define _HL	{`_H, `_L}
+`define _SP	{`_SPH, `_SPL}
+`define _PC	{`_PCH, `_PCL}
 
-`define STATE_FETCH			2'h0
-`define STATE_DECODE			2'h1
+`define FLAG_Z	8'b10000000
+`define FLAG_N	8'b01000000
+`define FLAG_H	8'b00100000
+`define FLAG_C	8'b00010000
+
+`define STATE_FETCH		2'h0
+`define STATE_DECODE		2'h1
 `define STATE_EXECUTE		2'h2
 `define STATE_WRITEBACK		2'h3
 
 `define INSN_LD_reg_imm8	8'b00xxx110
-`define INSN_HALT				8'b01110110
+`define INSN_HALT		8'b01110110
 `define INSN_LD_HL_reg		8'b01110xxx
 `define INSN_LD_reg_HL		8'b01xxx110
 `define INSN_LD_reg_reg		8'b01xxxxxx
+`define INSN_LD_reg_imm16	8'b00xx0001
+`define INSN_LD_SP_HL		8'b11111001
+`define INSN_PUSH_reg		8'b11xx0101
+`define INSN_POP_reg		8'b11xx0001
+`define INSN_LDH_AC		8'b111x0010	// Either LDH A,(C) or LDH (C),A
+`define INSN_LDx_AHL		8'b001xx010	// LDD/LDI A,(HL) / (HL),A
+`define INSN_ALU8		8'b10xxxxxx	// 10 xxx yyy
+`define INSN_NOP		8'b00000000
+`define INSN_RST		8'b11xxx111
+`define INSN_RET		8'b110x1001	// 1 = RETI, 0 = RET
+`define INSN_RETCC		8'b110xx000
+`define INSN_CALL		8'b11001101
+`define INSN_CALLCC		8'b110xx100	// Not that call/cc.
+`define INSN_JP_imm		8'b11000011
+`define INSN_JPCC_imm		8'b110xx010
+`define INSN_ALU_A		8'b00xxx111
+`define INSN_JP_HL		8'b11101001
+`define INSN_JR_imm		8'b00011000
+`define INSN_JRCC_imm		8'b001xx000
+`define INSN_INCDEC16		8'b00xxx011
+`define INSN_VOP_INTR		8'b11111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
+`define INSN_DI			8'b11110011
+`define INSN_EI			8'b11111011
+
+`define INSN_cc_NZ		2'b00
+`define INSN_cc_Z		2'b01
+`define INSN_cc_NC		2'b10
+`define INSN_cc_C		2'b11
+
 `define INSN_reg_A		3'b111
 `define INSN_reg_B		3'b000
 `define INSN_reg_C		3'b001
@@ -33,16 +81,47 @@
 `define INSN_reg_E		3'b011
 `define INSN_reg_H		3'b100
 `define INSN_reg_L		3'b101
-`define INSN_reg_dHL	3'b110
+`define INSN_reg_dHL		3'b110
+`define INSN_reg16_BC		2'b00
+`define INSN_reg16_DE		2'b01
+`define INSN_reg16_HL		2'b10
+`define INSN_reg16_SP		2'b11
+`define INSN_stack_AF		2'b11
+`define INSN_stack_BC		2'b00
+`define INSN_stack_DE		2'b01
+`define INSN_stack_HL		2'b10
+`define INSN_alu_ADD		3'b000
+`define INSN_alu_ADC		3'b001
+`define INSN_alu_SUB		3'b010
+`define INSN_alu_SBC		3'b011
+`define INSN_alu_AND		3'b100
+`define INSN_alu_XOR		3'b101
+`define INSN_alu_OR		3'b110
+`define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
+`define INSN_alu_RLCA		3'b000
+`define INSN_alu_RRCA		3'b001
+`define INSN_alu_RLA		3'b010
+`define INSN_alu_RRA		3'b011
+`define INSN_alu_DAA		3'b100
+`define INSN_alu_CPL		3'b101
+`define INSN_alu_SCF		3'b110
+`define INSN_alu_CCF		3'b111
+
+`define EXEC_INC_PC 		`_PC <= `_PC + 1;
+`define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
+`define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
+`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end
 
 module GBZ80Core(
 	input clk,
 	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
 	inout [7:0] busdata,
-	output reg buswr, output reg busrd);
+	output reg buswr, output reg busrd,
+	input irq, input [7:0] jaddr);
 	
-	reg [1:0] state = 0;					/* State within this bus cycle (see STATE_*). */
-	reg [2:0] cycle = 0;					/* Cycle for instructions. */
+	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
+	reg [2:0] cycle;					/* Cycle for instructions. */
 	
 	reg [7:0] registers[11:0];
 	
@@ -51,214 +130,103 @@ module GBZ80Core(
 	reg [7:0] opcode;				/* Opcode from the current machine cycle. */
 	
 	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
-	reg rd = 1, wr = 0, newcycle = 1;
+	reg rd, wr, newcycle;
 	
-	reg [7:0] tmp;					/* Generic temporary reg. */
+	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
 	
 	reg [7:0] buswdata;
 	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
 	
+	reg ie, iedelay;
+	
 	initial begin
-		registers[ 0] = 0;
-		registers[ 1] = 0;
-		registers[ 2] = 0;
-		registers[ 3] = 0;
-		registers[ 4] = 0;
-		registers[ 5] = 0;
-		registers[ 6] = 0;
-		registers[ 7] = 0;
-		registers[ 8] = 0;
-		registers[ 9] = 0;
-		registers[10] = 0;
-		registers[11] = 0;
+		registers[ 0] <= 0;
+		registers[ 1] <= 0;
+		registers[ 2] <= 0;
+		registers[ 3] <= 0;
+		registers[ 4] <= 0;
+		registers[ 5] <= 0;
+		registers[ 6] <= 0;
+		registers[ 7] <= 0;
+		registers[ 8] <= 0;
+		registers[ 9] <= 0;
+		registers[10] <= 0;
+		registers[11] <= 0;
+		rd <= 1;
+		wr <= 0;
+		newcycle <= 1;
+		state <= 0;
+		cycle <= 0;
+		busrd <= 0;
+		buswr <= 0;
+		busaddress <= 0;
+		ie <= 0;
+		iedelay <= 0;
+		opcode <= 0;
+		state <= `STATE_WRITEBACK;
+		cycle <= 0;
 	end
 
 	always @(posedge clk)
 		case (state)
 		`STATE_FETCH: begin
-			if (wr)
-				buswdata <= wdata;
-			if (newcycle)
+			if (newcycle) begin
 				busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
-			else
+				buswr <= 0;
+				busrd <= 1;
+			end else begin
 				busaddress <= address;
-			buswr <= wr;
-			busrd <= rd;
+				buswr <= wr;
+				busrd <= rd;
+				if (wr)
+					buswdata <= wdata;
+			end
 			state <= `STATE_DECODE;
 		end
 		`STATE_DECODE: begin
 			if (newcycle) begin
-				opcode <= busdata;
+				if (ie && irq)
+					opcode <= `INSN_VOP_INTR;
+				else
+					opcode <= busdata;
 				rdata <= busdata;
 				newcycle <= 0;
 				cycle <= 0;
-			end else
+			end else begin
 				if (rd) rdata <= busdata;
+				cycle <= cycle + 1;
+			end
+			if (iedelay) begin
+				ie <= 1;
+				iedelay <= 0;
+			end
 			buswr <= 0;
 			busrd <= 0;
+			wr <= 0;
+			rd <= 0;
+			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
+			wdata <= 8'bxxxxxxxx;
 			state <= `STATE_EXECUTE;
 		end
 		`STATE_EXECUTE: begin
-`define EXEC_INC_PC \
-	{registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEXTADDR_PCINC \
-	address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEWCYCLE \
-	newcycle <= 1; rd <= 1; wr <= 0
 			casex (opcode)
-			`INSN_LD_reg_imm8: begin
-				case (cycle)
-				0:	begin
-						`EXEC_INC_PC;
-						`EXEC_NEXTADDR_PCINC;
-						rd <= 1;
-					end
-				1: begin
-						`EXEC_INC_PC;
-						if (opcode[5:3] == `INSN_reg_dHL) begin
-							address <= {registers[`REG_H], registers[`REG_L]};
-							wdata <= rdata;
-							rd <= 0;
-							wr <= 1;
-						end else begin
-							`EXEC_NEWCYCLE;
-						end
-					end
-				2: begin
-						`EXEC_NEWCYCLE;
-					end
-				endcase
-			end
-			`INSN_HALT: begin
-				`EXEC_NEWCYCLE;
-				/* XXX Interrupts needed for HALT. */
-			end
-			`INSN_LD_HL_reg: begin
-				case (cycle)
-				0:	begin
-						case (opcode[2:0])
-						`INSN_reg_A:	begin wdata <= registers[`REG_A]; end
-						`INSN_reg_B:	begin wdata <= registers[`REG_B]; end
-						`INSN_reg_C:	begin wdata <= registers[`REG_C]; end
-						`INSN_reg_D:	begin wdata <= registers[`REG_D]; end
-						`INSN_reg_E:	begin wdata <= registers[`REG_E]; end
-						`INSN_reg_H:	begin wdata <= registers[`REG_H]; end
-						`INSN_reg_L:	begin wdata <= registers[`REG_L]; end
-						endcase
-						address <= {registers[`REG_H], registers[`REG_L]};
-						wr <= 1; rd <= 0;
-					end
-				1:	begin
-						`EXEC_INC_PC;
-						`EXEC_NEWCYCLE;
-					end
-				endcase
-			end
-			`INSN_LD_reg_HL: begin
-				case(cycle)
-				0: begin
-						address <= {registers[`REG_H], registers[`REG_L]};
-						wr <= 0; rd <= 1;
-					end
-				1: begin
-						tmp <= rdata;
-						`EXEC_INC_PC;
-						`EXEC_NEWCYCLE;
-					end
-				endcase
-			end
-			`INSN_LD_reg_reg: begin
-				`EXEC_INC_PC;
-				`EXEC_NEWCYCLE;
-				case (opcode[2:0])
-				`INSN_reg_A:	begin tmp <= registers[`REG_A]; end
-				`INSN_reg_B:	begin tmp <= registers[`REG_B]; end
-				`INSN_reg_C:	begin tmp <= registers[`REG_C]; end
-				`INSN_reg_D:	begin tmp <= registers[`REG_D]; end
-				`INSN_reg_E:	begin tmp <= registers[`REG_E]; end
-				`INSN_reg_H:	begin tmp <= registers[`REG_H]; end
-				`INSN_reg_L:	begin tmp <= registers[`REG_L]; end
-				endcase
-			end
+			`define EXECUTE
+			`include "allinsns.v"
+			`undef EXECUTE
+			default:
+				$stop;
 			endcase
 			state <= `STATE_WRITEBACK;
 		end
 		`STATE_WRITEBACK: begin
 			casex (opcode)
-				`INSN_LD_reg_imm8:
-					case (cycle)
-					0: cycle <= 1;
-					1: case (opcode[5:3])
-						`INSN_reg_A:	begin registers[`REG_A] <= rdata; cycle <= 0; end
-						`INSN_reg_B:	begin registers[`REG_B] <= rdata; cycle <= 0; end
-						`INSN_reg_C:	begin registers[`REG_C] <= rdata; cycle <= 0; end
-						`INSN_reg_D:	begin registers[`REG_D] <= rdata; cycle <= 0; end
-						`INSN_reg_E:	begin registers[`REG_E] <= rdata; cycle <= 0; end
-						`INSN_reg_H:	begin registers[`REG_H] <= rdata; cycle <= 0; end
-						`INSN_reg_L:	begin registers[`REG_L] <= rdata; cycle <= 0; end
-						`INSN_reg_dHL:	cycle <= 2;
-						endcase
-					2: cycle <= 0;
-					endcase
-				`INSN_HALT: begin
-					/* Nothing needs happen here. */
-					/* XXX Interrupts needed for HALT. */
-				end
-				`INSN_LD_HL_reg: begin
-					case (cycle)
-					0: cycle <= 1;
-					1: cycle <= 0;
-					endcase
-				end
-				`INSN_LD_reg_HL: begin
-					case (cycle)
-					0:	cycle <= 1;
-					1:	begin
-							case (opcode[5:3])
-							`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
-							`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
-							`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
-							`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
-							`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
-							`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
-							`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
-							endcase
-							cycle <= 0;
-						end
-					endcase
-				end
-				`INSN_LD_reg_reg: begin
-					case (opcode[5:3])
-					`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
-					`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
-					`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
-					`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
-					`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
-					`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
-					`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
-					endcase
-				end
+			`define WRITEBACK
+			`include "allinsns.v"
+			`undef WRITEBACK
+			default:
+				$stop;
 			endcase
 			state <= `STATE_FETCH;
 		end
 		endcase
 endmodule
-
-`timescale 1ns / 1ps
-module TestBench();
-	reg clk = 0;
-	wire [15:0] addr;
-	wire [7:0] data;
-	wire wr, rd;
-	reg [7:0] rom [2047:0];
-	
-	initial $readmemh("rom.hex", rom);
-	always #10 clk <= ~clk;
-	GBZ80Core core(
-		.clk(clk),
-		.busaddress(addr),
-		.busdata(data),
-		.buswr(wr),
-		.busrd(rd));
-	assign data = rd ? rom[addr] : 8'bzzzzzzzz;
-endmodule