X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/f2e0471561f022000caa932bbe012edde964b6eb..00e30b4dd08f216cc9fe89295f575b9b7d0622b5:/GBZ80Core.v diff --git a/GBZ80Core.v b/GBZ80Core.v index 738bf91..1d06b12 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -26,6 +26,11 @@ `define INSN_LD_HL_reg 8'b01110xxx `define INSN_LD_reg_HL 8'b01xxx110 `define INSN_LD_reg_reg 8'b01xxxxxx +`define INSN_LD_reg_imm16 8'b00xx0001 +`define INSN_LD_SP_HL 8'b11111001 +`define INSN_PUSH_reg 8'b11xx0101 +`define INSN_POP_reg 8'b11xx0001 +`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 `define INSN_reg_C 3'b001 @@ -34,7 +39,14 @@ `define INSN_reg_H 3'b100 `define INSN_reg_L 3'b101 `define INSN_reg_dHL 3'b110 - +`define INSN_reg16_BC 2'b00 +`define INSN_reg16_DE 2'b01 +`define INSN_reg16_HL 2'b10 +`define INSN_reg16_SP 2'b11 +`define INSN_stack_AF 2'b11 +`define INSN_stack_BC 2'b00 +`define INSN_stack_DE 2'b01 +`define INSN_stack_HL 2'b10 module GBZ80Core( input clk, output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */ @@ -59,18 +71,18 @@ module GBZ80Core( assign busdata = buswr ? buswdata : 8'bzzzzzzzz; initial begin - registers[ 0] = 0; - registers[ 1] = 0; - registers[ 2] = 0; - registers[ 3] = 0; - registers[ 4] = 0; - registers[ 5] = 0; - registers[ 6] = 0; - registers[ 7] = 0; - registers[ 8] = 0; - registers[ 9] = 0; - registers[10] = 0; - registers[11] = 0; + registers[ 0] <= 0; + registers[ 1] <= 0; + registers[ 2] <= 0; + registers[ 3] <= 0; + registers[ 4] <= 0; + registers[ 5] <= 0; + registers[ 6] <= 0; + registers[ 7] <= 0; + registers[ 8] <= 0; + registers[ 9] <= 0; + registers[10] <= 0; + registers[11] <= 0; end always @(posedge clk) @@ -96,6 +108,10 @@ module GBZ80Core( if (rd) rdata <= busdata; buswr <= 0; busrd <= 0; + wr <= 0; + rd <= 0; + address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened. + wdata <= 8'bxxxxxxxx; state <= `STATE_EXECUTE; end `STATE_EXECUTE: begin @@ -158,7 +174,7 @@ module GBZ80Core( case(cycle) 0: begin address <= {registers[`REG_H], registers[`REG_L]}; - wr <= 0; rd <= 1; + rd <= 1; end 1: begin tmp <= rdata; @@ -180,64 +196,244 @@ module GBZ80Core( `INSN_reg_L: begin tmp <= registers[`REG_L]; end endcase end + `INSN_LD_reg_imm16: begin + `EXEC_INC_PC; + case (cycle) + 0: begin + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 1: begin + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 2: begin `EXEC_NEWCYCLE; end + endcase + end + `INSN_LD_SP_HL: begin + case (cycle) + 0: begin + tmp <= registers[`REG_H]; + end + 1: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + tmp <= registers[`REG_L]; + end + endcase + end + `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */ + case (cycle) + 0: begin + wr <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; + case (opcode[5:4]) + `INSN_stack_AF: wdata <= registers[`REG_A]; + `INSN_stack_BC: wdata <= registers[`REG_B]; + `INSN_stack_DE: wdata <= registers[`REG_D]; + `INSN_stack_HL: wdata <= registers[`REG_H]; + endcase + end + 1: begin + wr <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; + case (opcode[5:4]) + `INSN_stack_AF: wdata <= registers[`REG_F]; + `INSN_stack_BC: wdata <= registers[`REG_C]; + `INSN_stack_DE: wdata <= registers[`REG_E]; + `INSN_stack_HL: wdata <= registers[`REG_L]; + endcase + end + 2: begin /* TWIDDLE OUR FUCKING THUMBS! */ end + 3: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end + endcase + end + `INSN_POP_reg: begin /* POP is 12 cycles! */ + case (cycle) + 0: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}; + end + 1: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}; + end + 2: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end + endcase + end + `INSN_LDH_AC: begin + case (cycle) + 0: begin + address <= {8'hFF,registers[`REG_C]}; + if (opcode[4]) begin // LD A,(C) + rd <= 1; + end else begin + wr <= 1; + wdata <= {8'hFF,registers[`REG_A]}; + end + end + 1: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end + endcase + end + default: + $stop; endcase state <= `STATE_WRITEBACK; end `STATE_WRITEBACK: begin casex (opcode) - `INSN_LD_reg_imm8: - case (cycle) - 0: cycle <= 1; - 1: case (opcode[5:3]) - `INSN_reg_A: begin registers[`REG_A] <= rdata; cycle <= 0; end - `INSN_reg_B: begin registers[`REG_B] <= rdata; cycle <= 0; end - `INSN_reg_C: begin registers[`REG_C] <= rdata; cycle <= 0; end - `INSN_reg_D: begin registers[`REG_D] <= rdata; cycle <= 0; end - `INSN_reg_E: begin registers[`REG_E] <= rdata; cycle <= 0; end - `INSN_reg_H: begin registers[`REG_H] <= rdata; cycle <= 0; end - `INSN_reg_L: begin registers[`REG_L] <= rdata; cycle <= 0; end - `INSN_reg_dHL: cycle <= 2; - endcase - 2: cycle <= 0; - endcase - `INSN_HALT: begin - /* Nothing needs happen here. */ - /* XXX Interrupts needed for HALT. */ - end - `INSN_LD_HL_reg: begin - case (cycle) - 0: cycle <= 1; - 1: cycle <= 0; - endcase - end - `INSN_LD_reg_HL: begin - case (cycle) - 0: cycle <= 1; - 1: begin - case (opcode[5:3]) - `INSN_reg_A: begin registers[`REG_A] <= tmp; end - `INSN_reg_B: begin registers[`REG_B] <= tmp; end - `INSN_reg_C: begin registers[`REG_C] <= tmp; end - `INSN_reg_D: begin registers[`REG_D] <= tmp; end - `INSN_reg_E: begin registers[`REG_E] <= tmp; end - `INSN_reg_H: begin registers[`REG_H] <= tmp; end - `INSN_reg_L: begin registers[`REG_L] <= tmp; end - endcase - cycle <= 0; - end - endcase - end - `INSN_LD_reg_reg: begin - case (opcode[5:3]) - `INSN_reg_A: begin registers[`REG_A] <= tmp; end - `INSN_reg_B: begin registers[`REG_B] <= tmp; end - `INSN_reg_C: begin registers[`REG_C] <= tmp; end - `INSN_reg_D: begin registers[`REG_D] <= tmp; end - `INSN_reg_E: begin registers[`REG_E] <= tmp; end - `INSN_reg_H: begin registers[`REG_H] <= tmp; end - `INSN_reg_L: begin registers[`REG_L] <= tmp; end + `INSN_LD_reg_imm8: + case (cycle) + 0: cycle <= 1; + 1: case (opcode[5:3]) + `INSN_reg_A: begin registers[`REG_A] <= rdata; cycle <= 0; end + `INSN_reg_B: begin registers[`REG_B] <= rdata; cycle <= 0; end + `INSN_reg_C: begin registers[`REG_C] <= rdata; cycle <= 0; end + `INSN_reg_D: begin registers[`REG_D] <= rdata; cycle <= 0; end + `INSN_reg_E: begin registers[`REG_E] <= rdata; cycle <= 0; end + `INSN_reg_H: begin registers[`REG_H] <= rdata; cycle <= 0; end + `INSN_reg_L: begin registers[`REG_L] <= rdata; cycle <= 0; end + `INSN_reg_dHL: cycle <= 2; endcase - end + 2: cycle <= 0; + endcase + `INSN_HALT: begin + /* Nothing needs happen here. */ + /* XXX Interrupts needed for HALT. */ + end + `INSN_LD_HL_reg: begin + case (cycle) + 0: cycle <= 1; + 1: cycle <= 0; + endcase + end + `INSN_LD_reg_HL: begin + case (cycle) + 0: cycle <= 1; + 1: begin + case (opcode[5:3]) + `INSN_reg_A: begin registers[`REG_A] <= tmp; end + `INSN_reg_B: begin registers[`REG_B] <= tmp; end + `INSN_reg_C: begin registers[`REG_C] <= tmp; end + `INSN_reg_D: begin registers[`REG_D] <= tmp; end + `INSN_reg_E: begin registers[`REG_E] <= tmp; end + `INSN_reg_H: begin registers[`REG_H] <= tmp; end + `INSN_reg_L: begin registers[`REG_L] <= tmp; end + endcase + cycle <= 0; + end + endcase + end + `INSN_LD_reg_reg: begin + case (opcode[5:3]) + `INSN_reg_A: begin registers[`REG_A] <= tmp; end + `INSN_reg_B: begin registers[`REG_B] <= tmp; end + `INSN_reg_C: begin registers[`REG_C] <= tmp; end + `INSN_reg_D: begin registers[`REG_D] <= tmp; end + `INSN_reg_E: begin registers[`REG_E] <= tmp; end + `INSN_reg_H: begin registers[`REG_H] <= tmp; end + `INSN_reg_L: begin registers[`REG_L] <= tmp; end + endcase + end + `INSN_LD_reg_imm16: begin + case (cycle) + 0: cycle <= 1; + 1: begin + case (opcode[5:4]) + `INSN_reg16_BC: registers[`REG_C] <= rdata; + `INSN_reg16_DE: registers[`REG_E] <= rdata; + `INSN_reg16_HL: registers[`REG_L] <= rdata; + `INSN_reg16_SP: registers[`REG_SPL] <= rdata; + endcase + cycle <= 2; + end + 2: begin + case (opcode[5:4]) + `INSN_reg16_BC: registers[`REG_B] <= rdata; + `INSN_reg16_DE: registers[`REG_D] <= rdata; + `INSN_reg16_HL: registers[`REG_H] <= rdata; + `INSN_reg16_SP: registers[`REG_SPH] <= rdata; + endcase + cycle <= 0; + end + endcase + end + `INSN_LD_SP_HL: begin + case (cycle) + 0: begin + cycle <= 1; + registers[`REG_SPH] <= tmp; + end + 1: begin + cycle <= 0; + registers[`REG_SPL] <= tmp; + end + endcase + end + `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */ + case (cycle) + 0: begin + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} - 1; + cycle <= 1; + end + 1: begin + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} - 1; + cycle <= 2; + end + 2: cycle <= 3; + 3: cycle <= 0; + endcase + end + `INSN_POP_reg: begin /* POP is 12 cycles! */ + case (cycle) + 0: begin + cycle <= 1; + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} + 1; + end + 1: begin + case (opcode[5:4]) + `INSN_stack_AF: registers[`REG_F] <= rdata; + `INSN_stack_BC: registers[`REG_C] <= rdata; + `INSN_stack_DE: registers[`REG_E] <= rdata; + `INSN_stack_HL: registers[`REG_L] <= rdata; + endcase + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} + 1; + cycle <= 2; + end + 2: begin + case (opcode[5:4]) + `INSN_stack_AF: registers[`REG_A] <= rdata; + `INSN_stack_BC: registers[`REG_B] <= rdata; + `INSN_stack_DE: registers[`REG_D] <= rdata; + `INSN_stack_HL: registers[`REG_H] <= rdata; + endcase + cycle <= 0; + end + endcase + end + `INSN_LDH_AC: begin + case (cycle) + 0: cycle <= 1; + 1: begin + cycle <= 0; + if (opcode[4]) + registers[`REG_A] <= rdata; + end + endcase + end endcase state <= `STATE_FETCH; end